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PRELIMINARY
Am186TMED/EDLV
High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n E86TM family 80C186- and 80C188-compatible microcontroller with enhanced bus interface - Lower system cost with higher performance - 3.3-V 0.3-V operation (Am186EDLV microcontrollers) n Programmable DRAM Controller - Supports zero-wait-state operation with 50-ns DRAM at 40 MHz, 60-ns @ 33 MHz, 70-ns @ 25 MHz - Includes programmable CAS-before-RAS refresh capability n High performance - 20-, 25-, 33-, and 40-MHz operating frequencies - Zero-wait-state operation at 40 MHz with 70-ns static memory - 1-Mbyte memory address space - 64-Kbyte I/O space n Enhanced features provide improved memory access and remove the requirement for a 2x clock input - Nonmultiplexed address bus - Processor operates at the clock input frequency - 8-bit or 16-bit programmable bus sizing including 8-bit boot option n Enhanced integrated peripherals - 32 programmable I/O (PIO) pins - Two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers - Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port - Improved serial port operation enhances 9-bit DMA support - Independent serial port baud rate generators - DMA to and from the serial ports - Watchdog timer can generate NMI or reset - A pulse-width demodulation option - A data strobe, true asynchronous bus interface option included for DEN - Reset configuration register Familiar 80C186 peripherals - Two independent DMA channels - Programmable interrupt controller with up to 8 external and 8 internal interrupts - Three programmable 16-bit timers - Programmable memory and peripheral chip-select logic - Programmable wait state generator - Power-save clock divider Software-compatible with the 80C186 and 80C188 microcontrollers with widely available native development tools, applications, and system software A compatible evolution of the Am186EM, Am186ES, and Am186ER microcontrollers Available in the following packages: - 100-pin, thin quad flat pack (TQFP) - 100-pin, plastic quad flat pack (PQFP)
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GENERAL DESCRIPTION
The Am186TMED/EDLV microcontrollers are part of the AMD E86TM family of embedded microcontrollers and microprocessors based on the x86 architecture. The Am186ED/EDLV microcontrollers are the ideal upgrade for 80C186/188 designs requiring 80C186/188 compatibility, increased performance, serial communications, a direct bus interface, and more than 64K of memory. The Am186ED/EDLV microcontrollers integrate a complete DRAM controller to take advantage of low DRAM costs. This reduces memory subsystem costs while maintaining SRAM performance.The Am186ED/EDLV microcontrollers also integrate the functions of a CPU, nonmultiplexed address bus, three timers, watchdog timer, chip selects, interrupt controller, two DMA controllers, two asynchronous serial ports, programmable bus
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sizing, and programmable I/O (PIO) pins on one chip. Compared to the 80C186/188 microcontrollers, the Am186ED/EDLV microcontrollers enable designers to reduce the size, power consumption, and cost of embedded systems, while increasing reliability, functionality, and performance. The Am186ED/EDLV microcontrollers have been designed to meet the most common requirements of embedded products developed for the communications, office automation, mass stor age, and general embedded markets. Specific applications include PBXs, multiplexers, modems, disk drives, hand-held and desktop terminals, fax machines, printers, photocopiers, and industrial controls.
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Publication# 21336 Rev: A Amendment/0 Issue Date: May 1997
PRELIMINARY
Am186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM
INT2/INTA0/PWD** INT3/INTA1/IRQ CLKOUTA INT6-INT4** INT1/SELECT INT0 TMROUT0 TMROUT1 PWD** TMRIN0 TMRIN1 DRQ0/INT5** DRQ1/INT6** NMI
CLKOUTB
X2 X1 VCC GND
Clock and Power Management Unit Watchdog Timer (WDT) Control Registers
Interrupt Control Unit
Pulse Width Demodulator (PWD)
Control Registers
Timer Control Unit 0 1 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers
DMA Unit 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
RES
ARDY SRDY S2/BTSEL S1-S0 DT/R DEN/DS HOLD HLDA S6/CLKDIV2 UZI
Control Registers
Refresh Control Unit
DRAM Control Unit
Bus Interface Unit
A19-A0
AD15-AD0
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WR ALE
RD WHB
R
Execution Unit
A
Chip-Select Unit
Control Registers
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PIO Unit Control Registers Asynchronous Serial Port 0 Asynchronous Serial Port 1
PIO31- PIO0*
TXD0 RXD0 RTS0/RTR0 CTS0/ENRX0 TXD1 RXD1 RTS1/RTR1** CTS1/ENRX1**
LCS/ONCE0/RAS0 MCS3/RAS1 MCS2/LCAS MCS1/UCAS PCS6/A2 PCS5/A1 PCS3-PCS0**
WLB
BHE/ADEN
MCS0 UCS/ONCE1
Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 21 and Table 2 on page 29 for information on shared functions. ** RTS1/RTR1 and CTS1/ENRX1 are multiplexed with PCS3 and PCS2, respectively. See the pin descriptions beginning on page 21.
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Am186ED/EDLV Microcontrollers
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Am186TMED/EDLV -40 K C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C= ED Commercial (TC =0C to +100C) C = EDLV Commercial (TC =0C to +70C) I = ED Industrial (TA =-40C to +85C) where: TC = case temperature where: TA = ambient temperature PACKAGE TYPE V=100-Pin Thin Quad Flat Pack (TQFP) K=100-Pin Plastic Quad Flat Pack (PQFP) SPEED OPTION -20 = 20 MHz -25 = 25 MHz -33 = 33 MHz -40 = 40 MHz
Valid Combinations Am186ED-20 Am186ED-25 Am186ED-33 Am186ED-40 Am186ED-20 Am186ED-25
Am186EDLV-20 Am186EDLV-25
Note: The industrial version of the Am186ED is offered only in the PQFP package.
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DEVICE NUMBER/DESCRIPTION Am186ED = High-Performance, 80C186-Compatible, 16-Bit Embedded Microcontroller Am186EDLV = High-Performance, 80L186-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller
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Valid Combinations
Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Note: The industrial version of the Am186ED as well as the Am186EDLV are available in 20 and 25 MHz operating frequencies only. The Am186ED and Am186EDLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies. Note: There is no 188 version of the Am186ED/ EDLV. The same 8-bit external bus capabilities can be achieved using the 8-bit boot capability and programmable bus sizing options.
Am186ED/EDLV Microcontrollers
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PRELIMINARY
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS ........................................................................................... 1 GENERAL DESCRIPTION .......................................................................................................... 1 AM186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM ................................................... 2 ORDERING INFORMATION ....................................................................................................... 3 Standard Products ........................................................................................................... 3 RELATED AMD PRODUCTS ...................................................................................................... 9 E86TM Family Devices ...................................................................................................... 9 Related Documents ....................................................................................................... 10 Third-Party Development Support Products .................................................................. 10 Customer Service .......................................................................................................... 10 KEY FEATURES AND BENEFITS ............................................................................................ 10 Application Considerations .............................................................................................11 COMPARING THE AM186ED/EDLV TO THE AM186ES/ESLV MICROCONTROLLERS ........ 12 Integrated DRAM Controller ........................................................................................... 12 Enhanced Refresh Control Unit ..................................................................................... 13 Option to Overlap DRAM with PCS ............................................................................... 13 Additional Serial Port Mode for DMA Support of 9-bit Protocols .................................... 13 Option to Boot from 8- or 16-bit Memory ....................................................................... 13 Improved External Bus Master Support ......................................................................... 13 PSRAM Controller Removed ......................................................................................... 13 TQFP CONNECTION DIAGRAMS AND PINOUTS .................................................................. 14 Top Side View--100-Pin Thin Quad Flat Pack (TQFP) ................................................. 14 TQFP PIN DESIGNATIONS ....................................................................................................... 15 Sorted by Pin Number .................................................................................................... 15 Sorted by Pin Name ....................................................................................................... 16 PQFP CONNECTION DIAGRAMS AND PINOUTS .................................................................. 17 Top Side View--100-Pin Plastic Quad Flat Pack (PQFP) ............................................. 17 PQFP PIN DESIGNATIONS ....................................................................................................... 18 Sorted by Pin Number .................................................................................................... 18 Sorted by Pin Name ....................................................................................................... 19 LOGIC SYMBOL--AM186ED/EDLV MICROCONTROLLERS ................................................. 20 PIN DESCRIPTIONS ................................................................................................................. 21 Pins That Are Used by Emulators .................................................................................. 21 Pin Terminology ............................................................................................................. 21 A19-A0 (A19/PIO9, A18/PIO8, A17/PIO7) .................................................................... 21 AD15-AD8 ..................................................................................................................... 21 AD7-AD0 ....................................................................................................................... 21 ALE ................................................................................................................................ 21 ARDY ............................................................................................................................. 22 BHE/ADEN ..................................................................................................................... 22 CLKOUTA ...................................................................................................................... 22 CLKOUTB ...................................................................................................................... 22 CTS0/ENRX0/PIO21 ...................................................................................................... 22 DEN/DS/PIO5 ................................................................................................................ 23 DRQ0/INT5/PIO12 ......................................................................................................... 23 DRQ1/INT6/PIO13 ......................................................................................................... 23 DT/R/PIO4 ..................................................................................................................... 23 GND ............................................................................................................................... 23 HLDA ............................................................................................................................. 23 HOLD ............................................................................................................................. 23 INT0 ............................................................................................................................... 24 INT1/SELECT ................................................................................................................ 24
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Am186ED/EDLV Microcontrollers
PRELIMINARY
INT2/INTA0/PWD/PIO31 ................................................................................................ 24 INT3/INTA1/IRQ ............................................................................................................. 24 INT4/PIO30 .................................................................................................................... 25 LCS/ONCE0/RAS0 ........................................................................................................ 25 MCS0/PIO14 .................................................................................................................. 25 MCS1/UCAS/PIO15 ....................................................................................................... 25 MCS2/LCAS/PIO24 ....................................................................................................... 25 MCS3/RAS1/PIO25 ....................................................................................................... 26 NMI ................................................................................................................................ 26 PCS1/PIO17, PCS0/PIO16 ............................................................................................ 26 PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 27 PCS3/RTS1/RTR1/PIO19 .............................................................................................. 27 PCS5/A1/PIO3 ............................................................................................................... 27 PCS6/A2/PIO2 ............................................................................................................... 28 PIO31-PIO0 (Shared) .................................................................................................... 28 RD .................................................................................................................................. 28 RES ................................................................................................................................ 28 RTS0/RTR0/PIO20 ........................................................................................................ 30 RXD0/PIO23 .................................................................................................................. 30 RXD1/PIO28 .................................................................................................................. 30 S2/BTSEL ...................................................................................................................... 30 S1-S0 ............................................................................................................................ 30 S6/CLKDIV2/PIO29 ....................................................................................................... 30 SRDY/PIO6 .................................................................................................................... 30 TMRIN0/PIO11 ............................................................................................................... 31 TMRIN1/PIO0 ................................................................................................................ 31 TMROUT0/PIO10 .......................................................................................................... 31 TMROUT1/PIO1 ............................................................................................................ 31 TXD0/PIO22 ................................................................................................................... 31 TXD1/PIO27 ................................................................................................................... 31 UCS/ONCE1 .................................................................................................................. 31 UZI/PIO26 ...................................................................................................................... 31 VCC ................................................................................................................................ 31 WHB ............................................................................................................................... 31 WLB ............................................................................................................................... 32 WR ................................................................................................................................. 32 X1 ................................................................................................................................... 32 X2 ................................................................................................................................... 32 FUNCTIONAL DESCRIPTION .................................................................................................. 33 Memory Organization ..................................................................................................... 33 I/O Space ....................................................................................................................... 33 BUS OPERATION ..................................................................................................................... 34 BUS INTERFACE UNIT ............................................................................................................. 36 Nonmultiplexed Address Bus ......................................................................................... 36 DRAM Address Multiplexing .......................................................................................... 36 Programmable Bus Sizing ............................................................................................. 37 Byte-Write Enables ........................................................................................................ 37 Data Strobe Bus Interface Option .................................................................................. 37 DRAM INTERFACE ................................................................................................................... 37 PERIPHERAL CONTROL BLOCK ............................................................................................ 38 Reading and Writing the PCB ........................................................................................ 38
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Am186ED/EDLV Microcontrollers
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PRELIMINARY
CLOCK AND POWER MANAGEMENT .................................................................................... 40 Phase-Locked Loop ....................................................................................................... 40 Crystal-Driven Clock Source .......................................................................................... 40 External Source Clock ................................................................................................... 41 System Clocks ............................................................................................................... 41 Power-Save Operation ................................................................................................... 41 Initialization and Processor Reset .................................................................................. 41 Reset Configuration Register ......................................................................................... 41 CHIP-SELECT UNIT .................................................................................................................. 42 Chip-Select Timing ......................................................................................................... 42 Ready and Wait-State Programming ............................................................................. 42 Chip-Select Overlap ....................................................................................................... 42 Upper Memory Chip Select ............................................................................................ 43 Low Memory Chip Select ............................................................................................... 43 Midrange Memory Chip Selects ..................................................................................... 43 Peripheral Chip Selects ................................................................................................. 43 REFRESH CONTROL UNIT ...................................................................................................... 44 INTERRUPT CONTROL UNIT .................................................................................................. 44 TIMER CONTROL UNIT ............................................................................................................ 45 Watchdog Timer ............................................................................................................. 45 PULSE WIDTH DEMODULATION ............................................................................................ 45 DIRECT MEMORY ACCESS .................................................................................................... 46 DMA Operation .............................................................................................................. 46 DMA Channel Control Registers .................................................................................... 47 DMA Priority ................................................................................................................... 47 ASYNCHRONOUS SERIAL PORTS ......................................................................................... 47 DMA Transfers through the Serial Port .......................................................................... 48 PROGRAMMABLE I/O (PIO) PINS ........................................................................................... 48 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 49 OPERATING RANGES ............................................................................................................. 49 DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES . 49 CAPACITANCE ......................................................................................................................... 50 POWER SUPPLY CURRENT ................................................................................................... 50 THERMAL CHARACTERISTICS ............................................................................................... 51 TQFP Package .............................................................................................................. 51 Typical Ambient Temperatures ....................................................................................... 52 COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS .. 57 Key to Switching Waveforms ......................................................................................... 57 Alphabetical Key to Switching Parameter Symbols ....................................................... 58 Numerical Key to Switching Parameter Symbols ........................................................... 61 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 64 Read Cycle (20 MHz and 25 MHz) ................................................................................ 64 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 65 Read Cycle (33 MHz and 40 MHz) ................................................................................ 65 READ CYCLE WAVEFORMS ................................................................................................... 66 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 67 Write Cycle (20 MHz and 25 MHz) ................................................................................ 67 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 68 Write Cycle (33 MHz and 40 MHz) ................................................................................ 68 WRITE CYCLE WAVEFORMS .................................................................................................. 69
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Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 70 DRAM ............................................................................................................................ 70 DRAM Read Cycle Timing with No-Wait States ............................................................ 71 DRAM Read Cycle Timing with Wait State(s) ................................................................ 71 DRAM Write Cycle Timing with No-Wait States ............................................................. 72 DRAM Write Cycle Timing With Wait State(s) ............................................................... 72 DRAM CAS-before-RAS Cycle Timing .......................................................................... 73 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 74 Interrupt Acknowledge Cycle (20 MHz and 25 MHz) ..................................................... 74 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 75 Interrupt Acknowledge Cycle (33 MHz and 40 MHz) ..................................................... 75 INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS ........................................................... 76 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 77 Software Halt Cycle (20 MHz and 25 MHz) ................................................................... 77 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 77 Software Halt Cycle (33 MHz and 40 MHz) ................................................................... 77 SOFTWARE HALT CYCLE WAVEFORMS ............................................................................... 78 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 79 Clock (20 MHz and 25 MHz) .......................................................................................... 79 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 80 Clock (33 MHz and 40 MHz) .......................................................................................... 80 CLOCK WAVEFORMS .............................................................................................................. 81 Clock Waveforms--Active Mode ................................................................................... 81 Clock Waveforms--Power-Save Mode .......................................................................... 81 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 82 Ready and Peripheral (20 MHz and 25 MHz) ................................................................ 82 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................. 82 Ready and Peripheral (33 MHz and 40 MHz) ................................................................ 82 SYNCHRONOUS, ASYNCHRONOUS, AND PERIPHERAL WAVEFORMS ............................ 83 Synchronous Ready Waveforms ................................................................................... 83 Asynchronous Ready Waveforms .................................................................................. 83 Peripheral Waveforms ................................................................................................... 83 SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES ............................................................................................... 84 Reset and Bus Hold (20 MHz and 25 MHz) ................................................................... 84 SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES ................ 84 Reset and Bus Hold (33 MHz and 40 MHz) ................................................................... 84 RESET AND BUS HOLD WAVEFORMS ................................................................................... 85 Reset Waveforms .......................................................................................................... 85 Signals Related to Reset Waveforms ............................................................................ 85 Bus Hold Waveforms--Entering .................................................................................... 86 Bus Hold Waveforms--Leaving ..................................................................................... 86 TQFP PHYSICAL DIMENSIONS ............................................................................................... 87 PQFP PHYSICAL DIMENSIONS .............................................................................................. 88
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Am186ED/EDLV Microcontrollers
7
PRELIMINARY
LIST OF FIGURES
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Am186ED Microcontroller Example System Design .............................................. 11 80C186 Microcontroller Example System Design ................................................. 12 Two-Component Address ...................................................................................... 33 16-Bit Mode--Normal Read and Write Operation ................................................. 34 16-Bit Mode--Read and Write with Address Bus Disable In Effect ....................... 35 8-Bit Mode--Normal Read and Write Operation ................................................... 35 8-Bit Mode--Read and Write with Address Bus Disable in Effect ......................... 36 Am186ED/EDLV Microcontrollers Oscillator Configurations ................................. 40 Clock Organization ................................................................................................ 41 DMA Unit Block Diagram ....................................................................................... 47 Typical Icc Versus Frequency for Am186EDLV Microcontroller ............................. 50 Typical Icc Versus Frequency for Am186ED Microcontroller ................................. 50 Thermal Resistance(C/Watt) ................................................................................ 51 Thermal Characteristics Equations ........................................................................ 51 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 53 Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 54 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 55 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 56
LIST OF TABLES
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17
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Data Byte Encoding ............................................................................................... 22 Numeric PIO Pin Designations .............................................................................. 29 Alphabetic PIO Pin Designations ........................................................................... 29 Bus Cycle Encoding ............................................................................................... 30 Segment Register Selection Rules ........................................................................ 33 DRAM Pin Interface ............................................................................................... 37 Programming the Bus Width of Am186ED/EDLV Microcontrollers ........................ 37 Peripheral Control Block Register Map .................................................................. 39 Am186ED/EDLV Microcontrollers Maximum DMA Transfer Rates ....................... 46 Typical Power Consumption Calculation for the Am186EDLV Microcontroller ...... 50 Thermal Characteristics (C/Watt) ......................................................................... 51 Typical Power Consumption Calculation ............................................................... 52 Junction Temperature Calculation ......................................................................... 52 Typical Ambient Temperatures (C) for PQFP with a 2-Layer Board .................... 53 Typical Ambient Temperatures (C) for TQFP with a 2-Layer Board .................... 54 Typical Ambient Temperatures (C) for PQFP with a 4-Layer to 6-Layer Board ... 55 Typical Ambient Temperatures (C) for TQFP with a 4-Layer to 6-Layer Board ... 56
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Am186ED/EDLV Microcontrollers
PRELIMINARY
Microprocessors AT Peripheral Microcontrollers 186 Peripheral Microcontrollers Am486 Future K86TM Future Am486DX Microprocessor Am386SX/DX Microprocessors ElanSC310 Microcontroller ElanSC300 Microcontroller Am186ES and Am188ES Microcontrollers Am186EM and Am188EM Microcontrollers Am186EMLV & Am188EMLV Microcontrollers Am186ESLV & Am188ESLV Microcontrollers Am186ER and Am188ER Microcontrollers ElanSC410 Microcontroller
32-bit Future Am186 and Am188 Future
ElanSC400 Microcontroller
Am186ED Microcontroller
80C186 and 80C188 Microcontrollers 80L186 and 80L188 Microcontrollers
Time
The E86 Family of Embedded Microprocessors and Microcontrollers
RELATED AMD PRODUCTS E86TM Family Devices
Device 80C186 80C188 80L186 80L188 Am186EM Am188EM Am186EMLV Am188EMLV
Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16bit external data bus Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM
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ElanTMSC300 ElanSC310 ElanSC400 ElanSC410 Am386(R)DX Am386(R)SX Am486(R)DX
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller Single-chip, PC/AT-compatible microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus Am186ED/EDLV Microcontrollers 9
PRELIMINARY
Related Documents
The following documents provide additional i n f o r m a t i o n r e g a r d i n g t h e A m 1 8 6 E D / E D LV microcontrollers: n Am186ED/EDLV Microcontrollers User's Manual, order # 21335 n Am186 and Am188 Family Instruction Set Manual, order # 21267 n FusionE86SM Catalog, order # 19255 n E86 Family Support Tools Brief, order # 20071 n FusionE86 Development Tools Reference CD, order # 21058
To d own lo ad do cu me nt s a nd s oft war e , ft p t o ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Questions, requests, and input concerning AMD's WWW pages can be sent via E-mail to webmaster@amd.com. Documentation and Literature Free E86 family information such as data books, user's man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering (800) 222-9323 (512) 602-5651 (512) 602-7639 (800) 222-9323 Toll-free for U.S. and Canada Direct dial worldwide
Third-Party Development Support Products
The FusionE86 S M Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-tomarket needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the worldwide staff of AMD field application engineers and factory support staff to answer E86 family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases.
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KEY FEATURES AND BENEFITS
The Am186ED/EDLV microcontrollers extend the AMD family of microcontrollers based on the industry-standard x86 architecture. The Am186ED/EDLV microcontrollers are a higher-performance, highly integrated version of the 80C186/188 microprocessors, offering an attractive migration path. In addition, the Am186ED/ EDLV microcontrollers offer application-specific features that can enhance the system functionality of the Am186ES/ESLV and Am188ES/ESLV microcontrollers. Upgrading to the Am186ED/EDLV microcontrollers is an attractive solution for several reasons: n Programmable DRAM controller--Enables system designers to take advantage of low-cost DRAM and fully utilize the performance and flexibility of the x86 architecture. The DRAM controller supports zero wait-state performance with 50-ns DRAM at 40 MHz, or, if required, can be programmed with wait states. The Am186ED/EDLV microcontrollers provide a CAS-before-RAS refresh unit. n Minimized total system cost--New and enhanced peripherals and on-chip system interface logic on the Am186ED/EDLV microcontrollers reduce the cost of existing 80C186/188 designs. n X86 software compatibility--80C186/188-compatible and upward-compatible with the other members of the AMD E86 family.
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fax
AMD Facts-On-DemandTM fax information service, tollfree for U.S. and Canada
For technical support questions on all E86 products, send E-mail to lpd.support@amd.com.
Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline
World Wide Web Home Page and FTP Site To access the AMD home page go to: http://www.amd.com.
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Am186ED/EDLV Microcontrollers
PRELIMINARY n Enhanced performance--The Am186ED/EDLV microcontrollers increase the performance of 80C186/188 systems, and the nonmultiplexed address bus offers unbuffered access to memory. n Enhanced functionality--The enhanced on-chip peripherals of the Am186ED/EDLV microcontrollers include two asynchronous serial ports, 32 PIOs, a watchdog timer, additional interrupt pins, a pulse width demodulation option, DMA directly to and from the serial ports, 8-bit and 16-bit programmable bus sizing, a 16-bit reset configuration register, and enhanced chip-select functionality. Clock Generation The integrated clock generation circuitry of the Am186ED/EDLV microcontrollers enables the use of a 1x crystal frequency. The Am186ED design in Figure 1 achieves 40-MHz CPU operation, while using a 40MHz crystal.
Application Considerations
The integration enhancements of the Am186ED/EDLV microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customerspecific peripherals and circuits within the upgraded design. Figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. Memory Interface The Am186ED/EDLV microcontrollers integrate a versatile memory controller which supports direct memory accesses to DRAM, SRAM, Flash, EPROM, and ROM. No external glue logic is required and all required control signals are provided. The peripheral chip selects have been enhanced to allow them to overlap the DRAM. This allows a small 1.5K portion of the DRAM memory space to be used for peripherals without bus contention. The improved memory timing specifications of the Am186ED/EDLV microcontrollers allow for zero-waitstate operation at 40 MHz using 50-ns DRAM, 70-ns SRAM, or 70-ns Flash memory. For 60-ns DRAM one wait state is required at 40 MHz and zero wait states at 33 MHz and below. For 70-ns DRAM two wait states are required at 40 MHz, one wait state at 33 MHz, and zero wait states at 25 MHz and below. This reduces overall system cost by enabling the use of commonly available memory speeds and taking advantage of DRAM's lower cost per bit over SRAM. Figure 1 also shows an implementation of an RS-232 console or modem communications port. The RS-232 to CMOS voltage-level converter is required for the electrical interface with the external device.
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Figure 1. Am186ED Microcontroller Example System Design
Direct Memory Interface Example Figure 1 illustrates the direct memory interface of the Am186ED microcontroller. The processor's A19-A0 bus connects to the memory address inputs, the AD bus connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. The odd A1-A17 address pins connect to the DRAM multiplexed address bus. The RD output connects to the DRAM Output Enable (OE) pin for read operations. Write operations use the WR output connected to the DRAM Write Enable (WE) pin. The UCAS and LCAS pins provide byte selection.
Am186ED/EDLV Microcontrollers
11
PRELIMINARY
COMPARING THE Am186ES/ESLV TO THE Am186ED/EDLV MICROCONTROLLERS
Compared to the Am186ES/ESLV microcontrollers, the Am186ED/EDLV microcontrollers have the following additional features: n Integrated DRAM controller n Enhanced refresh control unit n Option to overlap DRAM with peripheral chip select (PCS) n Additional serial port mode for DMA support of 9-bit protocols n Option to boot from 8- or 16-bit memory n Improved external bus master support n PSRAM controller removed Figure 1 shows an example system using a 40-MHz Am 1 86 ED mi c r oc o nt r ol le r. F i gu r e 2 s ho ws a comparable system implementation with an 80C186. Because of its superior integration, the Am186ED/ EDLV system does not require the support devices that are required on the 80C186 example system. In addition, the Am186ED/EDLV microcontrollers provide significantly better performance with its 40-MHz clock rate.
Integrated DRAM Controller
The integrated DRAM controller directly interfaces DRAM to support no-wait state DRAM interface up to 40 MHz. Wait states can be inserted to support slower DRAM. All signals requir ed by the DRAM ar e generated on the Am186ED/EDLV microcontrollers and no external logic is r equired. The DRAM multiplexed address pins are connected to the odd address pins starting with A1 on the Am186ED/EDLV microcontrollers to MA0 on the DRAM. The correct row and column addresses are generated on these pins during a DRAM access. The UCAS and LCAS are used to select which byte of the DRAM is accessed during a read or write. The RAS0 controls the lower bank of DRAM which starts at 00000h in the address map and is bounded by the lower memory size selected in the LMCS register. RAS1 controls the upper bank of DRAM which ends at FFFFFh and is bounded by the upper memory size in the UMCS register. When RAS1 is enabled, UCS is automatically disabled. Neither, either, or both DRAM banks can be activated.
25
D
12
R
A
T F
Figure 2. 80C186 Microcontroller Example System Design
Am186ED/EDLV Microcontrollers
PRELIMINARY
Enhanced Refresh Control Unit
The refresh control unit (RCU) is enhanced with two additional bits in the refresh counter to allow for longer refresh periods. The address generated during a refresh has been fixed to FFFFFh. When either bank of DRAM is enabled and the RCU is enabled, a CASbefore-RAS refresh will be generated based on the time period coded into the refresh counter.
entire memory map can be set to 16-bit or 8-bit or mixed between 8-bit and 16-bit based on the USIZ, LSIZ, MSIZ, and IOSIZ bits in the AUXCON register.
Improved External Bus Master Support
When the bus is arbitrated away from the Am186ED/ EDLV microcontrollers using the HOLD pin, the chip selects are driven High (negated) and then held High with an internal ~10-kohm pullup. This allows external bus masters to assert the chip selects by externally pulling them Low, without having to combine the chip selects from the Am186ED/EDLV microcontrollers and the external bus master in logic external to the Am186ED/EDLV microcontrollers. This internal pullup is activated for any bus arbitration, even if the pin is being used as a PIO input.
Option to Overlap DRAM with PCS
The peripheral chip selects (PCS0-PCS6) can overlap DRAM blocks with different wait states without external or internal bus contention. The RAS0 or RAS1 will assert along with the appropriate PCS. The UCAS and LCAS will not assert, preventing the DRAM from writing erroneously or driving the data bus during a read. The PCS must have the same or higher number of wait states than the DRAM. The PCS bus width will be determined by the LSIZ or USIZ bus widths as programmed in the AUXCON register.
PSRAM Controller Removed
The PSRAM mode found on the Am186ES/ESLV microcontrollers has been removed and replaced with a DRAM controller. This includes removal of the variant PSRAM LCS timing and refresh strobe on MCS3.
Additional Serial Port Mode for DMA Support of 9-bit Protocols
A mode 7 was added to the serial port which enhances the direct memory access (DMA) support for 9-bit protocols. Using mode 2, the serial port can be programmed to interrupt only if the 9th bit is set, ignoring all 9th bit cleared byte receptions. Mode 3 receives all bytes, whether the 9th bit is set or cleared. Mode 7 also receives all bytes whether the 9th bit is set or cleared, but now an interrupt is generated when the 9th bit is set. This allows the DMA to service all receptions, but also allows the CPU to intervene when the trailer (9th bit set) is received. In all modes using DMA, the interrupts other than transmitter ready and character received interrupts can still be generated. This allows the DMA to handle the standard sending and receiving characters while the CPU can intervene when a non-standard event (e.g., framing error) occurs.
Option to Boot from 8- or 16-bit Memory
The Am186ED/EDLV microcontrollers can boot from 8or 16-bit-wide non-volatile memory, based on the state of the S2/BTSEL pin. If S2/BTSEL is pulled High or left floating, an internal pullup sets the boot mode option to 16-bit. If S2/BTSEL is pulled resistively Low during reset, the boot mode option is for 8-bit. The status of the S2/BTSEL pin is latched on the rising edge of reset. If the 8-bit boot option is selected, the width of the memory region associated with UCS can be changed in the AUXCON register. This allows for cheaper 8-bitwide memory to be used for booting the microcontroller, while speed-critical code and data can be executed from 16-bit-wide lower memory. Eight-bit or 16-bit-wide peripherals can be used in the memory area between LCS and UCS or in the I/O space. The Am186ED/EDLV Microcontrollers 13
D
R
A
T F
PRELIMINARY
TQFP CONNECTION DIAGRAMS AND PINOUTS Am186ED/EDLV Microcontrollers Top Side View--100-Pin Thin Quad Flat Pack (TQFP)
PCS2 /CTS1/ENRX1 PCS3 /RTS1/RTR1 PCS 6/A2 LCS / ONCE 0/RAS0
MCS3/ RAS1 MCS2/LCAS VCC
DRQ0/INT5 DRQ1/INT6
100 99
98 97
96 95
94 93
92 91
90 89
88 87
86 85
84 83
VCC PCS 5/A1
82 81
80 79
UCS / ONCE1 INT0
PCS0
PCS1 GND
RES GND
78
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
INT2/INTA 0/PWD INT3/INTA 1/IRQ
INT1/ SELECT
TMRIN0 TMROUT0
TMROUT1 TMRIN1
AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 V CC AD14 AD7 AD15 S6/CLKDIV2 UZI TXD1 RXD1 CTS0/ENRX0 RXD0 TXD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Am186ED/EDLV Microcontrollers
D
21 22 23 24 25 26 27 RTS0/RTR0 BHE/ADEN
19 20
R
30 31 32 33 34 35 S2/BTSEL S1 S0
A
38 39 40 41 VCC CLKOUTA
T F
44 45 46 47 48 49 VCC A17 A16 A15 A14 A13 A12 50
INT4 MCS1/UCAS MCS0 DEN/DS DT/R NMI SRDY HOLD HLDA WLB WHB GND A0 A1 VCC A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
28 29
36 37
GND X1 X2
Note: Pin 1 is marked for orientation.
14
Am186ED/EDLV Microcontrollers
CLKOUTB GND A19 A18
WR RD ALE ARDY
42 43
PRELIMINARY
TQFP PIN DESIGNATIONS--Am186ED/EDLV Microcontrollers Sorted by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 Name AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 Pin No. 26 27 28 29 30 31 32 33 34 35 Name RTS0/RTR0/ PIO20 BHE/ADEN WR RD ALE ARDY S2/BTSEL S1 S0 GND Pin No. 51 52 53 54 55 56 57 58 59 60 Name A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin No. 76 77 78 79 80 81 82 83 84 85 Name INT3/INTA1/IRQ INT2/INTA0/PWD/ PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0/ RAS0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AD5 GND AD13 AD6 VCC AD14 AD7 AD15
36 37 38 39 40 41
X1 X2 VCC CLKOUTA CLKOUTB GND
61 62 63
VCC A1
S6/CLKDIV2/PIO29 UZI/PIO26
TXD1/PIO27
RXD1/PIO28
CTS0/ENRX0/PIO21 RXD0/PIO23 TXD0/PIO22
D
R
42 43 44 VCC 45 46 A16 47 48 49 50 A15 A14 A13 A12
A19/PIO9 A18/PIO8
A
64 65 66 67 68 69 70 71 72 73 74 75
A0 GND
WHB WLB HLDA HOLD
T F
PCS3/RTS1/ RTR1/ PIO19 86 87 88 GND PCS1/PIO17 PCS0/PIO16 89 90 91 92 93 94 95 96 97 98 99 100 VCC GND RES
PCS2/CTS1/ ENRX1/PIO18
MCS2/LCAS/ PIO24 MCS3/RAS1/ PIO25
SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14 MCS1/UCAS/ PIO15 INT4/PIO30
A17/PIO7
TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/INT6/PIO13 DRQ0/INT5/PIO12
Am186ED/EDLV Microcontrollers
15
PRELIMINARY
TQFP PIN DESIGNATIONS--Am186ED/EDLV Microcontrollers Sorted by Pin Name
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 No. 11 14 17 2 4 6 8 10 13 16 18 30 31 27 39 40 23 72 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/PWD/ PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0/RAS0 MCS0/PIO14 MCS1/UCAS/ PIO15 MCS2/LCAS/PIO24 No. 87 93 67 68 79 78 77 76 75 Pin Name RXD1 S0 S1 S2/BTSEL S6/CLKDIV2/ PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/ PIO10 No. 22 34 33 32 19 69 98 95 97 96
D
42 1 3 5 7 9
DRQ0/INT5/PIO12
DRQ1/INT6/PIO13 DT/R/PIO4
R
A
NMI PCS0/PIO16 PCS1/PIO17 PCS2/CTS1/ ENRX1/PIO18 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RXD0/PIO23
MCS3/RAS1/PIO25
T F
81 TMROUT1/PIO1 73 TXD0/PIO22 TXD1 74 91 UCS/ONCE1 UZI/PIO26 VCC 92 70 89 88 86 85 83 82 29 94 26 24 VCC VCC VCC VCC VCC WHB WLB WR X1 X2
25
21 80 20 15 38 44 61 84 90 65 66 28 36
100 99 71
PCS3/RTS1/RTR1/ PIO19
GND GND GND
12 35 41 64
RTS0/RTR0/PIO20
GND
37
16
Am186ED/EDLV Microcontrollers
PRELIMINARY
PQFP CONNECTION DIAGRAMS AND PINOUTS Am186ED/EDLV Microcontrollers Top Side View--100-Pin Plastic Quad Flat Pack (PQFP)
CTS0/ENRX0 RXD1 TXD1 UZI
S6/CLKDIV2
AD12 AD4
AD7 AD14
AD15
AD13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
AD11 AD3
GND AD5
VCC AD6
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RXD0 TXD0 RTS0/RTR0 BHE/ADEN WR RD ALE ARDY S2/BTSEL S1 S0 GND X1 X2 V CC CLKOUTA CLKOUTB GND A19 A18 V CC A17 A16 A15 A14 A13 A12 A11 A10 A9
D
31 32 33 A8 A7 A6
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AD10 AD2 AD9
Am186ED/EDLV Microcontrollers
R
A5 A4 A3 A2
A
HOLD HLDA WHB WLB
T F
DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND PCS0 PCS1 GND DEN/DS MCS0 NMI DT/R
AD1 AD8 AD0
MCS3/RAS1
MCS2/LCAS VCC
PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 VCC PCS5/A1 PCS6/A2 LCS/ONCE0/RAS0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD INT3/INTA1/IRQ INT4 MCS1/UCAS
Note: Pin 1 is marked for orientation.
Am186ED/EDLV Microcontrollers
SRDY
VCC A1 A0 GND
17
PRELIMINARY
PQFP PIN DESIGNATIONS--Am186ED/EDLV Microcontrollers Sorted by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name RXD0/PIO23 TXD0/PIO22 RTS0/RTR0/ PIO20 BHE/ADEN WR RD ALE ARDY S2/BTSEL S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name MCS1/UCAS/PIO15 INT4/PIO30 INT3/INTA1/IRQ INT2/INTA0/PWD/ PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0/RAS0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC Pin No. 76 77 78 79 80 81 82 83 84 85 Name DRQ1/INT6/PIO13 DRQ0/INT5/PIO12 AD0 AD8 AD1 AD9 AD2 AD10 AD3
PCS3/RTS1/RTR1/ PIO19 PCS2/CTS1/ ENRX1/PIO18 GND
A17/PIO7 A16 A15
A14
D
R
WLB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14
WHB
A
65 66 67 68 VCC 69 70 GND 71 72 73 74 75 RES
PCS1/PIO17 PCS0/PIO16
T F
AD11 AD4 86 87 AD12 88 AD5 89 GND 90 AD13 AD6 91 92 93 94 95 96 97 98 99 100 VCC AD14 AD7 AD15 S6/CLKDIV2/PIO29 UZI/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0/ENRX0/PIO21
MCS2/LCAS/PIO24 MCS3/RAS1/PIO25
TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11
18
Am186ED/EDLV Microcontrollers
PRELIMINARY
PQFP PIN DESIGNATIONS--Am186ED/EDLV Microcontrollers Sorted by Pin Name
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 No. 88 91 94 79 81 83 85 87 90 93 95 7 8 4 16 17 100 49 77 76 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/ PWD/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0/RAS0 MCS0/PIO14 MCS1/UCAS/PIO15 MCS2/LCAS/PIO24 MCS3/RAS1/PIO25 NMI No. 70 89 44 45 56 55 54 53 52 Pin Name RXD1/PIO28 S0 S1 S2/BTSEL S6/CLKDIV2/ PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/ PIO10 No. 99 11 10 9 96 46 75 72 74 73 2
PCS0/PIO16 PCS1/PIO17
DRQ0/INT5/PIO12 DRQ1/INT6/PIO13 DT/R/PIO4
D
78 80 82 84 86
GND GND GND
R
48 12 18 41 64
PCS2/CTS1/ENRX1/ PIO18 PCS3/RTS1/RTR1/ PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RTS0/RTR0/PIO20 RXD0/PIO23
A
T F
58 TMROUT1/PIO1 50 TXD0/PIO22 51 TXD1/PIO27 68 UCS/ONCE1 UZI/PIO26 VCC VCC VCC 69 47 66 65 63 62 60 59 6 71 3 1 VCC VCC VCC WHB WLB WR X1 X2
98
57 97 15 21 38 61 67 92 42 43 5 13 14
GND
Am186ED/EDLV Microcontrollers
19
PRELIMINARY
LOGIC SYMBOL--Am186ED/EDLV MICROCONTROLLERS
X1 Clocks X2 CLKOUTA CLKOUTB RES DRQ1/INT6 DRQ0/INT5 INT4 INT3/INTA1/IRQ INT2/INTA0/PWD * Address and Address/Data Buses * * 20 16 A19-A0 AD15-AD0 S6/CLKDIV2 UZI ALE S2/BTSEL 2 S1-S0 HOLD HLDA RD WR Bus Control * * DT/R DEN/DS ARDY * SRDY PCS6/A2 PCS5/A1 PCS3/RTS1/RTR1 PCS2/CTS1/ENRX1 PCS1-PCS0 LCS/ONCE0/RAS0 INT1/SELECT INT0 NMI * * Reset Control and Interrupt Service
MCS3/RAS1
BHE/ADEN
Timer Control
D
* * * * 32 shared **
WHB WLB
R
A
MCS2/LCAS
MCS1/UCAS
MCS0
T F
* * * * 2 * * * * * * DMA Control * * * * * * * *
*
Memory and Peripheral Control
UCS/ONCE1
DRQ1/INT6 DRQ0/INT5
TXD0 RXD0 CTS0/ENRX0 RTS0/RTR0 TXD1 RXD1
TMRIN0 TMROUT0 TMRIN1 TMROUT1
Asynchronous Serial Port Control
Programmable I/O Control
PCS2/CTS1/ENRX1 PIO32-PIO0 PCS3/RTS1/RTR1
Notes: * These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 21 and Table 2 on page 29 for information on shared function. ** All PIO signals are shared with other physical pins.
20
Am186ED/EDLV Microcontrollers
PRELIMINARY
PIN DESCRIPTIONS Pins That Are Used by Emulators
The following pins are used by emulators: A19-A0, AD7-AD0, ALE, BHE/ADEN, CLKOUTA, RD, S2-S0, S6/CLKDIV2, and UZI. Many emulators require S6/CLKDIV2 and UZI to be configured in their normal functionality as S6 and UZI, not as PIOs. If BHE/ADEN is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality.
system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is deasserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15-AD0) can also be used to load system configuration information into the internal reset configuration register. When accesses are made to 8-bit-wide memory regions, AD15-AD8 drive their corresponding address signals throughout the access. If the disable address phase and 8-bit mode are selected (see the ADEN description with the BHE/ADEN pin), then AD15-AD8 are three-stated during t 1 and driven with their corresponding address signal from t2 to t4.
Pin Terminology
The following terms are used to describe the pins: Input--An input-only pin. Output--An output-only pin. Input/Output--A pin that can be either input or output (I/O). Synchronous--Synchronous inputs must meet setup and hold times in relation to CLKOUTA. Synchronous outputs are synchronous to CLKOUTA. Asynchronous--Inputs or outputs that are asynchronous to CLKOUTA.
AD7-AD0
Address and Data Bus (input/output, three-state, synchronous, level-sensitive)
A19-A0 (A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O addresses to the system one half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15-AD0). During a bus hold or reset condition, the address bus is in a high-impedance state. While the Am186ED/EDLV microcontrollers are directly connected to DRAM, A19-A0 will serve as the nonmultiplexed address bus for SRAM, FLASH, PROM, EPROM, and peripherals. The odd address pins (A17, A15, A13, A11, A9, A7, A5, A3, and A1) will have both the row and column address during a DRAM space access. The odd address signals connect directly to the row and column multiplexed address bus of the DRAM. The even address pins (A18, A16, A14, A12, A10, A8, A6, A4, A2, and A0) and A19 will have the initial address asserted during the full DRAM access. These signals will not transition during a DRAM access.
D
R
A
ALE
These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. This bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t1), and it supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). In 8-bit mode, AD7- AD0 supplies the data for both high and low bytes. The address phase of these pins can be disabled. See the ADEN pin description with the BHE/ADEN pin. When WLB is deasserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15-AD0) can also be used to load system configuration information into the internal reset configuration register.
T F
Address Latch Enable (output, synchronous) This pin indicates to the system that an address appears on the address and data bus (AD15-AD0). The address is guaranteed to be valid on the trailing edge of ALE. This pin is three-stated during ONCE mode. ALE is three-stated and held resistively Low during a bus hold condition. In addition, ALE has a weak internal pulldown resistor that is active during reset, so that an external device does not get a spurious ALE during reset. 21
AD15-AD8
Address and Data Bus (input/output, three-state, synchronous, level-sensitive) AD15-AD8--These time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It supplies data to the
Am186ED/EDLV Microcontrollers
PRELIMINARY
ARDY
Asynchronous Ready (input, asynchronous, level-sensitive) This pin is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin is asynchronous to CLKOUTA and is active High. To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period can be added. To a l w a y s a s s e r t t h e r e a d y c o n d i t i o n t o t h e microcontroller, tie ARDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
not drive the address during t1. There is a weak internal pullup resistor on BHE/ADEN so no external pullup is required. Disabling the address phase reduces power consumption. If BHE/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. The pin is sampled on the rising edge of RE S . ( S 6 an d U Z I a l s o a s s u me th e i r n o r m al functionality in this instance. See Table 2 on page 29.) The internal pullup on ADEN is ~9 kohm.
Note: For 8-bit accesses, AD15-AD8 are driven with addresses during the t2-t4 bus cycle, regardless of the setting of the DA bit in the UMCS and LMCS registers.
CLKOUTA
Clock Output A (output, synchronous) This pin supplies the internal clock to the system. Depending on the value of the system configuration register (SYSCON), CLKOUTA operates at either the PLL frequency (X1), the power-save frequency, or is held Low. CLKOUTA remains active during reset and bus hold conditions. All AC timing specs that use a clock relate to CLKOUTA.
BHE/ADEN
Bus High Enable (three-state, output, synchronous) Address Enable (input, internal pullup) BHE--During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN and AD0 pins are encoded as shown in Table 1.
Table 1. Data Byte Encoding
BHE 0 0 1 1 AD0 0 1 0 1 Type of Bus Cycle Word Transfer High Byte Transfer (Bits 15-8) Low Byte Transfer (Bits 7-0) Reserved
BHE is asserted during t 1 and remains asserted through t3 and tW. BHE does not need to be latched. BHE floats during bus hold and reset. WLB and WHB implement the functionality of BHE and AD0 for High and Low byte-write enables. UCAS and LCAS implement High and Low-byte selection for DRAM devices. BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0 are High. During refresh cycles, the A bus is indeterminate and the AD bus is driven to FFFFh during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. ADEN--If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus (AD15-AD0) is enabled or disabled during LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the AD bus will
D
R
A
CLKOUTB
Clock Output B (output, synchronous)
This pin supplies an additional clock with a delayed output compared to CLKOUTA. Depending upon the value of the system configuration register (SYSCON), CLKOUTB operates at either the PLL frequency (X1), the power-save frequency, or is held Low. CLKOUTB remains active during reset and bus hold conditions. CLKOUTB is not used for AC timing specs.
T F
CTS0/ENRX0/PIO21
Clear-to-Send 0 (input, asynchronous) Enable-Receiver-Request 0 (input, asynchronous) CTS0--This pin provides the Clear-to-Send signal for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The CTS0 signal gates the transmission of data from the associated serial port transmit register. When CTS0 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS0 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS0 is checked only at the beginning of the transmission of the frame. ENRX0--This pin provides the Enable Receiver Request for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial
22
Am186ED/EDLV Microcontrollers
PRELIMINARY port 0 control register is set). The ENRX0 signal enables the receiver for the associated serial port. INT6 is edge-triggered only and must be held until the interrupt is acknowledged.
DEN/DS/PIO5
Data Enable (output, three-state, synchronous) Data Strobe (output, three-state, synchronous) DEN--This pin supplies an output enable to an external data-bus transceiver. DEN is asserted during memory, I/O, and interrupt acknowledge cycles. DEN is deasserted when DT/R changes state. DEN floats during a bus hold or reset condition. DS--The data strobe provides a signal where the write cycle timing is identical to the read cycle timing. When used with other control signals, DS provides an interface for 68K-type peripherals without the need for additional system interface logic. When DS is asserted, addresses are valid. When DS is asserted on writes, data is valid. When DS is asserted on reads, data can be asserted on the AD bus.
DT/R/PIO4
Data Transmit or Receive (output, three-state, synchronous) This pin indicates in which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the microcontroller transmits data. When this pin is deasserted Low, the microcontroller receives data. DT/R floats during a bus hold or reset condition.
GND
Ground Ground pins connect the microcontroller to the system ground.
HLDA
Bus Hold Acknowledge (output, synchronous) This pin is asserted High to indicate to an external bus master that the microcontroller has released control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress. It then relinquishes control of the bus to the external bus master by asserting HLDA and floating DEN, RD, WR, S2-S0, AD15-AD0, S6, A19-A0, BHE, WHB, WLB, and DT/R. The following chip selects are three-stated (then will be held High with an ~10-kohm resistor): UCS, LCS, MCS3-MCS0, PCS6-PCS5, PCS3-PCS0, RAS0, RAS1, UCAS, and LCAS. ALE is also threestated (then will be held Low with an ~10-kohm resistor). When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (for example, to refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams for bus hold on page 86.
Note: This pin resets to DEN.
DRQ0/INT5/PIO12
DMA Request 0 (input, synchronous, level-sensitive) Maskable Interrupt Request 5 (input, asynchronous, edge-triggered) DRQ0--This pin indicates to the microcontroller that an external device is ready for DMA channel 0 to perform a transfer. DRQ0 is level-triggered and internally synchronized. DRQ0 is not latched and must remain active until serviced. INT5--If DMA 0 is not enabled or DMA 0 is not being used with external synchronization, INT5 can be used as an additional external interrupt request. INT5 shares the DMA 0 interrupt type (0Ah) and register control bits. INT5 is edge-triggered only and must be held until the interrupt is acknowledged.
DRQ1/INT6/PIO13
DMA Request 1 (input, synchronous, level-sensitive) Maskable Interrupt Request 6 (input, asynchronous, edge-triggered) DRQ1--This pin indicates to the microcontroller that an external device is ready for DMA channel 1 to perform a transfer. DRQ1 is level-triggered and internally synchronized. DRQ1 is not latched and must remain active until serviced. INT6--If DMA 1 is not enabled or DMA 1 is not being used with external synchronization, INT6 can be used as an additional external interrupt request. INT6 shares the DMA 1 interrupt type (0Bh) and register control bits.
D
R
A
HOLD
T F
Bus Hold Request (input, synchronous, level-sensitive) This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186ED/EDLV microcontrollers' HOLD latency time, that is, the time between HOLD request and HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM
Am186ED/EDLV Microcontrollers
23
PRELIMINARY refresh requests in priority of activity requests received by the processor. For more information, see the HLDA pin description on page 23. interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode. INTA0--When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. PWD--If pulse width demodulation is enabled, PWD processes a signal through the Schmitt trigger. PWD is used internally to drive TIMERIN0 and INT2, and PWD is inverted internally to drive TIMERIN1 and INT4. If INT2 and INT4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating PWD signal can be calculated by comparing the values in timer 0 and timer 1. In PW D mo de, th e s i gn al s TIM ER IN0 /P IO 11 , TIMERIN1/PIO0, and INT4/PIO30 can be used as PIOs. If they are not used as PIOs, they are ignored internally. The level of INT2/INTA0/PWD/PIO31 is reflected in the PIO data register for PIO31 as if it was a PIO.
INT0
Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) INT1--This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged. SELECT--When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus.
INT2/INTA0/PWD/PIO31
Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) Pulse Width Demodulator (input, Schmitt trigger) INT2--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee
D
R
A
INT3/INTA1/IRQ
Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table.
T F
Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1--When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. IRQ--When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
24
Am186ED/EDLV Microcontrollers
PRELIMINARY
INT4/PIO30
Maskable Interrupt Request 4 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged. When pulse width demodulation mode is enabled, the INT4 signal is used internally to indicate a High-to-Low transition on the PWD signal. When pulse width demodulation mode is enabled, INT4/PIO30 can be used as a PIO.
MCS0/PIO14
Midrange Memory Chip Select 0 (output, synchronous, internal pullup) This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS0 can be programmed as the chip select for the entire middle chip select address range. This mode is recommended when using DRAM since the MCS1, MCS2, and MCS3 chip selects function as RAS and CAS signals for the DRAM interface and are not available as chip selects. MCS0 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS0 is three-stated and held resistively High during a bus hold condition. In addition, MCS0 has a weak internal pullup resistor that is active during reset.
LCS/ONCE0/RAS0
Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) Row Address Strobe 0 LCS--This pin indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbytes. LCS is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. LCS is three-stated and held resistively High during a bus hold condition. In addition, LCS has an ~9-kohm internal pullup resistor that is active during reset. ONCE0--During reset, this pin and ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode; otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE0 has a weak internal pullup resistor that is active only during reset. RAS0--This pin is the row address strobe for the lower DR A M b l o c k . T h e s el e c t i o n o f R A S 0 o r L C S functionality, along with their configurations, are set using the LMCS register. RAS0 is three-stated and held resistively High during a bus hold condition. In addition, RAS0 has a weak internal pullup resistor that is active during reset.
MCS1/UCAS/PIO15
Midrange Memory Chip Select (output, synchronous, internal pullup) Upper Column Address Strobe
D
R
A
This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS1 is configured for 8-bit or 16-bit bus size via the auxiliary configuration register. MCS1 is three-stated and held resistively High during a bus hold condition. In addition, MCS1 has a weak internal pullup resistor that is active during reset. If MCS0 is programmed to be active for the entire middle chip-select range, then this signal is available as a PIO or a DRAM control. If this signal is not programmed as a PIO or DRAM control and if MCS0 is programmed for the entire middle chip-select range, this signal operates normally. UCAS--When either bank of DRAM is activated, the UCAS functionality is enabled. The UCAS activates when the DRAM access is for the AD15-AD8 byte. UCAS also activates at the start of a DRAM refresh access.
T F
UCAS is three-stated and held resistively High during a bus hold condition. In addition, UCAS has a weak internal pullup resistor that is active during reset.
MCS2/LCAS/PIO24
Midrange Memory Chip Select (output, synchronous, internal pullup) Lower Column Address Strobe This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of
Am186ED/EDLV Microcontrollers
25
PRELIMINARY the midrange memory block are programmable. MCS2 is configured for 8-bit or 16-bit bus size via the auxiliary configuration register. MCS2 is three-stated and held resistively High during a bus hold condition. In addition, it has a weak internal pullup resistor that is active during reset. If MCS0 is programmed to be active for the entire middle chip-select range, then this signal is available as a PIO or a DRAM control. If this pin is not programmed as a PIO or DRAM control and if MCS0 is programmed for the whole middle chip-select range, this signal operates normally. LCAS--When either bank of DRAM is activated, the LCAS functionality is enabled. The LCAS activates when the DRAM access is for the AD7-AD0 byte. LCAS also activates at the start of a DRAM refresh access. LCAS is three-stated and held resistively High during a bus hold condition. In addition, LCAS has a weak internal pullup resistor that is active during reset.
NMI
Nonmaskable Interrupt (input, synchronous, edge-sensitive) This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT6-INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine, via the STI instruction for example, the fact that an NMI is currently in service does not have any effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI should not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period.
MCS3/RAS1/PIO25
Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Row Address Strobe 1 (output, synchronous) MCS3--This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the mid-range memory block are programmable. MCS3 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS3 is three-stated and held resistively High during a bus hold condition. In addition, this pin has a weak internal pullup resistor that is active during reset. If MCS0 is programmed for the entire middle chipselect range, then this signal is available as a PIO or a DRAM control. If MCS3 is not programmed as a PIO or DRAM control and if MCS0 is programmed for the entire middle chip-select range, this signal operates normally. RAS1--This pin is the row address strobe for the upper DR AM b l oc k . T h e se l ec t i on o f R A S 1 o r U CS functionality, along with their configurations, are set using the UMCS register. When RAS1 is activated, the code activating RAS1 must not reside in the UCS memory block. When RAS1 is activated, UCS is automatically deactivated and remains negated. RAS1 is three-stated and held resistively High during a bus hold condition. In addition, RAS1 has a weak internal pullup resistor that is active during reset.
D
R
A
T F
PCS1/PIO17, PCS0/PIO16
Peripheral Chip Selects (output, synchronous) These pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable.
The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM they overlap. The PCS signals take precedence over DRAM accesses when DRAM and memory-mapped peripherals overlap. PCS1-PCS0 are three-stated and held resistively High during a bus hold condition. In addition, PCS1-PCS0 each have a weak internal pullup resistor that is active during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range
26
Am186ED/EDLV Microcontrollers
PRELIMINARY covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. PCS0-PCS1 also have extended wait state options.
PCS3/RTS1/RTR1/PIO19
Peripheral Chip Select 3 (output, synchronous) Ready-to-Send 1 (output, asynchronous) Ready-to-Receive 1 (output, asynchronous) PCS3--This pin provides the Peripheral Chip Select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM they overlap. The PCS signals take precedence over DRAM accesses when DRAM and memory-mapped peripherals overlap. PCS3 is three-stated and held resistively High during a bus hold condition. In addition, PCS3 has a weak internal pullup resistor that is active during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. PCS3 also has extended wait state options. RTS1--This pin provides the Ready-to-Send signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTS1 signal is asserted when the associated serial port transmit register contains data which has not been transmitted.
PCS2/CTS1/ENRX1/PIO18
Peripheral Chip Select 2 (output, synchronous) Clear-to-Send 1 (input, asynchronous) Enable-Receiver-Request 1 (input, asynchronous) PCS2--This pin provides the Peripheral Chip Select 2 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS2 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM they overlap. The PCS signals take precedence over DRAM accesses when DRAM and memory-mapped peripherals overlap. PCS2 is three-stated and held resistively High during a bus hold condition. In addition, PCS2 has a weak internal pullup resistor that is active during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. PCS2 also has extended wait state options. CTS1--This pin provides the Clear-to-Send signal for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The CTS1 signal gates the transmission of data from the associated serial port transmit register. When CTS1 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS1 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS1 is checked only at the beginning of the transmission of the frame.
D
R
A
T F
RTR1--This pin provides the Ready-to-Receive signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTR1 signal is asserted when the associated serial port receive register does not contain valid, unread data.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous) Latched Address Bit 1 (output, synchronous) PCS5--This pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM
ENRX1--This pin provides the Enable Receiver Request for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The ENRX1 signal enables the receiver for the associated serial port.
Am186ED/EDLV Microcontrollers
27
PRELIMINARY they overlap. The PCS signals take precedence over DRAM accesses when DRAM and memory-mapped peripherals overlap. PCS5 is three-stated and held resistively High during a bus hold condition. In addition, PCS5 has a weak internal pullup resistor that is active during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. PCS5 also has extended wait state options. A1--When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. During a bus hold condition, A1 retains its previously latched value. pullup or pulldown. The pins that are multiplexed with PIO31-PIO0 are listed in Table 2 and Table 3. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 lists the defaults for the PIOs. Most of the PIO pins are configured as PIO inputs with pullup after power-on reset. The system initialization code must reconfigure any PIO pins as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. PIO15 and PIO24 should be set to normal operation before enabling either bank of DRAM. PIO25 should be set to normal operation before enabling the upper bank of DRAM.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous) Latched Address Bit 2 (output, synchronous) PCS6--This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. The PCS chip selects can overlap either block of DRAM. The PCS chip selects must have the same or greater number of wait states as the bank of DRAM they overlap. The PCS signals take precedence over DRAM accesses when DRAM and memory-mapped peripherals overlap. PCS6 is three-stated and held resistively High during a bus hold condition. In addition, PCS6 has a weak internal pullup resistor that is active during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. PCS6 also has extended wait state options. A2--When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value.
RD
Read Strobe (output, synchronous, three-state) RD--This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed to not be asserted before the address and data bus is floated during the address-todata transition. RD floats during a bus hold condition.
D
R
A
RES
Reset (input, asynchronous, level-sensitive) This pin requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h. RES must be held Low for at least 1 ms.
T F
RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLK O UTA mu st b e s tab le fo r m or e th an fo ur CLKOUTA periods during which RES is asserted. The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network.
PIO31-PIO0 (Shared)
Programmable I/O Pins (input/output, asynchronous, open-drain) The Am186ED/EDLV microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak 28 Am186ED/EDLV Microcontrollers
PRELIMINARY Table 2. Numeric PIO Pin Designations
PIO No 0 1 2 3 4 5 6 7 9
(1)
Table 3.
Associated Pin A17(1) A18
(1)
Alphabetic PIO Pin Designations
PIO No Power-On Reset Status 7 8 9 21 5 12 13 4 31 30 14 15 24 25 Normal operation(3) Normal operation(3) Normal operation(3) Input with pullup Normal operation(3) Input with pullup Input with pullup Normal operation(3) Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
Associated Pin TMRIN1 TMROUT1 PCS6/A2 PCS5/A1 DT/R DEN/DS SRDY A17 A18 A19 TMROUT0 TMRIN0 DRQ0/INT5 DRQ1/INT6 MCS0 MCS1/UCAS PCS0 PCS1 PCS3/RTS1/RTR1 RTS0/RTR0 CTS0/ENRX0 TXD0 RXD0 MCS2/LCAS MCS3/RAS1 UZI TXD1 RXD1 INT4
Power-On Reset Status Input with pullup Input with pulldown Input with pullup Input with pullup Normal operation(3) Normal operation(3) Normal operation
(4) (3)
A19(1) CTS0/ENRX0 DEN/DS DRQ0/INT5 DRQ1/INT6 DT/R INT2/INTA0/PWD INT4 MCS0 MCS1/UCAS MCS2/LCAS MCS3/RAS1 PCS0 PCS1
Normal operation Normal operation Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
8(1)
(1)
Normal operation(3)
(3)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
(1,2)
Input with pulldown
PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 PCS5/A1
PCS2/CTS1/ENRX1 Input with pullup
Input with pullup
27 28 29
(1,2)
S6/CLKDIV2
30 31
INT2/INTA0/PWD
Notes:
The following notes apply to both tables. 1. These pins are used by many emulators. (Emulators also use S2-S0, RES, NMI, CLKOUTA, BHE, ALE, AD15- AD0, and A16-A0.) 2. These pins revert to normal operation if BHE/ADEN is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available.
D
Input with pullup Input with pullup Input with pullup
R
A
PCS6/A2 RTS0/RTR0 RXD0 RXD1 S6/CLKDIV2 SRDY TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD0 TXD1 UZI
(1,2)
T F
16 17 18 19 3 2 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup 20 Input with pullup Input with pullup Input with pullup 23 28 6 11 0 10 1 22 27 26 29 Input with pullup Normal operation(4) Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup
(1,2)
Input with pullup
Am186ED/EDLV Microcontrollers
29
PRELIMINARY
RTS0/RTR0/PIO20
Ready-to-Send 0 (output, asynchronous) Ready-to-Receive 0 (output, asynchronous) RTS0--This pin provides the Ready-to-Send signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTS0 signal is asserted when the associated serial port transmit register contains data that has not been transmitted. RTR0--This pin provides the Ready-to-Receive signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTR0 signal is asserted when the associated serial port receive register does not contain valid, unread data.
S1-S0
Bus Cycle Status (output, three-state, synchronous) These pins indicate to the system the type of bus cycle in progress. S1 can be used as a data transmit or receive indicator. S1-S0 float during bus hold and hold acknowledge conditions. The S2-S0 pins are encoded as shown in Table 4.
Table 4.
S2/BTSEL 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1
Bus Cycle Encoding
S0 0 1 0 1 0 1 0 1 Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch
RXD0/PIO23
Receive Data 0 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 0.
RXD1/PIO28
Receive Data 1 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 1.
S6/CLKDIV2/PIO29
S2/BTSEL
Bus Cycle Status (output, three-state, synchronous) Boot Mode Select
S2--This pin indicates to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/O indicator. S2-S0 float during bus hold and hold acknowledge conditions. The S2-S0 pins are encoded as shown in Table 4. BTSEL--The Am186ED/EDLV microcontrollers can boot from 8- or 16-bit wide nonvolatile memory, based on the state of the BTSEL pin. If BTSEL is pulled High or left floating, an internal pullup sets the boot mode option to 16-bit. If BTSEL is pulled resistively Low during reset, the 8-bit boot mode option is selected. The status of the BTSEL pin is latched on the rising edge of reset. If 8-bit mode is selected, the width of the memory region associated with UCS can be changed in the AUXCON register. This signal should never be tied to VCC or VSS directly since this pin is driven during normal operation. This signal should be tied Low with an external resistor if the 8-bit boot mode is to be used. The internal pullup resistor on BTSEL is ~9 kohm.
D
R
A
Bus Cycle Status Bit 6 (output, synchronous) Clock Divide by 2 (input, internal pullup)
S6--During the second and remaining periods of a cycle (t2, t3, and t4), this pin is asserted High to indicate a DMA-initiated bus cycle. During a bus hold or reset condition, S6 floats.
T F
None (passive)
Read data from memory Write data to memory
CLKDIV2--If S6/CLKDIV2/PIO29 is held Low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. If this mode is selected, the PLL is disabled. The pin is sampled on the rising edge of RES. If S6 is to be used as PIO29 in input mode, the device driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input with pullup, so the pin does not need to be driven High externally.
SRDY/PIO6
Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the
30
Am186ED/EDLV Microcontrollers
PRELIMINARY microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS--This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is three-stated and held resistively High during a bus hold condition. In addition, UCS has an ~9-kohm internal pullup resistor that is active during reset. After reset, UCS is active for the 64 Kbyte memory range from F0000h to FFFFFh, including the reset address of FFFF0h. When RAS1 is activated, the code activating RAS1 must not reside in the UCS memory block. When RAS1 is activated, UCS is automatically deactivated and remains negated. This allows code to boot from UCS, copy its code to another memory device, then activate a DRAM bank in place of the UCS memory block. ONCE1--During reset, this pin and LCS/ONCE0 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE1 has a weak internal pullup resistor that is active only during a reset.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 0. After internally synchronizing a Low-to-High transition on TMRIN0, the microcontroller increments the timer. TMRIN0 must be tied High if not being used. When PIO11 is enabled, TMRIN0 is pulled High internally. TMRIN0 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN0/PIO11 pin can be used as a PIO when pulse width demodulation mode is enabled.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used. When PIO0 is enabled, TMRIN1 is pulled High internally. TMRIN1 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN1/PIO0 pin can be used as a PIO when pulse width demodulation mode is enabled.
TMROUT0/PIO10
Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT0 is floated during a bus hold or reset.
TMROUT1/PIO1
Timer Output 1 (output, synchronous)
This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT1 floats during a bus hold or reset.
TXD0/PIO22
Transmit Data 0 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 0.
D
R
A
VCC WHB
T F
UZI/PIO26
Upper Zero Indicate (output, synchronous) This pin lets the designer determine if an access to the interrupt vector table is in progress by ORing it with bits 15-10 of the address and data bus (AD15-AD10). UZI is the logical AND of the inverted A19-A16 bits. It asserts in the first period of a bus cycle and is held throughout the cycle.
Power Supply (input) These pins supply power (+5 V) to the microcontroller.
TXD1/PIO27
Transmit Data 1 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 1.
Write High Byte (output, three-state, synchronous) This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated.
Am186ED/EDLV Microcontrollers
31
PRELIMINARY WHB is asserted with AD15-AD8. WHB is the logical OR of BHE and WR. This pin floats during reset.
WLB
Write Low Byte (output, three-state, synchronous) WLB--This pin and WHB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WLB is asserted with AD7-AD0. WLB is the logical OR of AD0 and WR. This pin floats during reset.
WR
Write Strobe (output, synchronous) WR--This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR floats during a bus hold or reset condition. WR should be used for DRAM write enable.
X1
Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected.
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin.
D
R
A
T F
32
Am186ED/EDLV Microcontrollers
PRELIMINARY
FUNCTIONAL DESCRIPTION
The Am186ED/EDLV microcontrollers are based on the architecture of the 80C186 and 80C188 microcontrollers. The Am186ED/EDLV microcontrollers function in the enhanced mode of earlier generations of 80C186 and 80C188 microcontrollers. Enhanced mode includes system features such as power-save control. Each of the 8086, 8088, 80186, and 80188 microcontrollers contains the same basic set of registers, instructions, and addressing modes. The Am186ED/ EDLV microcontrollers are backward-compatible with the 80C186 and 80C188 microcontrollers. A full description of all the Am186ED/EDLV microcontroller registers and instructions is included in the Am186ED/EDLV Microcontrollers User's Manual, order# 21335A.
1 19 0 0 15 2 0 2 2 A
ment register used for physical address generation is implied by the addressing mode used (see Table 5).
Shift Left 4 Bits
1 15 0 15
2
A
0
2
4 Segment Logical 0 Base Address 2 Offset 0
4
0 0 2 0
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the seg1 19
A
6
To Memory
Figure 3. Two-Component Address
Memory Reference Needed Instructions Local Data Stack
D
Table 5.
Segment Register Used Code (CS) Data (DS) Stack (SS) Extra (ES)
R
A
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended such that A15-A8 are Low. I/O port addresses 00F8h through 00FFh are reserved.
T F
2 Physical Address 0
Segment Register Selection Rules
Implicit Segment Selection Rule Instructions (including immediate data) All data references All stack pushes and pops; any memory references that use BP Register All string instruction references that use the DI Register as an index
External Data (Global)
Am186ED/EDLV Microcontrollers
33
PRELIMINARY
BUS OPERATION
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186ED/EDLV microcontrollers continue to provide the multiplexed AD bus and, in addition, provides a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1-t4). For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus during the normal address portion of the bus cycle for accesses to RAS0, RAS1, UCS, and/or LCS address spaces. In this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the UMCS and LMCS registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. In 8-bit mode, the address is driven on AD15-AD8 during the data portion of the bus cycle regardless of the setting of the DA bits. If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus for all accesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers' multiplexed address bus and providing support for existing emulation tools. The following diagrams show the bus cycles of the Am186ED/EDLV microcontrollers when the address bus disable feature is in effect: Figure 4 shows the affected signals during a normal read or write operation for 16-bit mode. The address and data are multiplexed onto the AD bus. Figure 5 shows a 16-bit mode bus cycle when address bus disable is in effect. This results in the AD bus operating in a nonmultiplexed address/data mode. The A bus has the address during a read or write operation. Figure 6 shows the affected signals during a normal read or write operation for 8-bit mode. The multiplexed address/data mode is compatible with the 80C186 and 80C188 microcontrollers and might be used to take advantage of existing logic or peripherals. Figure 7 shows an 8-bit mode bus cycle when address bus disable is in effect. The address and data are not multiplexed. The AD7-AD0 signals have only data on the bus, while the AD bus has the address during a read or write operation.
D
CLKOUTA A19-A0 AD15-AD0 (Read) AD15-AD0 (Write) LCS or UCS or MCSx, PCSx
R
t1
Address Phase
A
t2 Address
T F
t4 Data
t3
Data Phase
Address
Address
Data
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics beginning on page 70.
Figure 4.
16-Bit Mode--Normal Read and Write Operation
34
Am186ED/EDLV Microcontrollers
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD15-AD0 (Read) AD15-AD0 (Write) LCS, or UCS or MCSx, PCSx
t2
t3 Data Phase
t4
Address
Data
Data
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics beginning on page 70.
Figure 5.
16-Bit Mode--Read and Write with Address Bus Disable In Effect
t1
CLKOUTA A19-A0
D
AD7-AD0 (Read) AD7-AD0 (Write) LCS or UCS or MCSx, PCSx
R
Address Phase
A
t2 Address
t3
Data Phase
T F
t4 Data
Address
AD15-AD8 (Read or Write)
Address
Address
Data
Figure 6.
8-Bit Mode--Normal Read and Write Operation
Am186ED/EDLV Microcontrollers
35
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD7-AD0 (Read)
t2
t3 Data Phase
t4
Address
Data
AD15-AD8 AD7-AD0 (Write) LCS, or UCS or MCSx, PCSx
Address
Data
Figure 7. 8-Bit Mode--Read and Write with Address Bus Disable in Effect
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the peripheral control block. The Am186ED/EDLV microcontrollers provide an enhanced bus interface unit with the following features: n A nonmultiplexed address bus n DRAM address multiplexing
n A static bus-sizing option for 8-bit and 16-bit memory and I/O n Separate byte write enables and CAS for High and Low bytes n Data strobe bus interface option The standard 80C186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. On the Am186ED/EDLV microcontrollers, new byte write enables, DRAM control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. The standard 80C186/188 microcontroller required external DRAM controller logic and DRAM address multiplex circuitry for interfacing to DRAM. On the Am186ED/EDLV microcontrollers, the integrated DRAM controller and internal address multiplexing can reduce design costs by eliminating this external logic.
D
R
A
Further, system costs can be reduced for systems using more than 64K of RAM by replacing SRAM with less expensive DRAM.
T F
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19-A0) is valid one-half CLKOUTA cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte-write enable signals, the A19-A0 bus provides a seamless interface to SRAM, and Flash EPROM memory systems.
DRAM Address Multiplexing
The A19-A0 address bus also provides the addresses for the DRAM. When RAS0 or RAS1 asserts for a read or write, all the address signals are valid. This allows the DRAM to latch the odd addresses into the row address. Before the UCAS and/or LCAS asserts, the odd addresses A17-A1 change to reflect the even addresses. This allows the DRAM to latch in the even addresses into the column address. During a refresh cycle, the entire A19-A0 address bus is stable but undefined. The internal address and that reflected on the AD bus is all 1s. The DRAM pin interface is shown in Table 6.
36
Am186ED/EDLV Microcontrollers
PRELIMINARY Table 6.
AM186ED/EDLV Microcontroller Pins A1 A3 A5 A7 A9 A11 A13 A15 A17 RAS0 RAS1 UCAS LCAS RD WR MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 RAS (Bank 0) RAS (Bank 1) UCAS (AD15-AD8 Byte) LCAS (AD7-AD0 Byte) OE WE
DRAM Pin Interface
DRAM Pin
Byte-Write Enables
The Am186ED/EDLV microcontrollers provide the WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte-write enables. WHB is the logical OR of BHE and WR. WHB is Low when BHE and WR are both Low. WLB is the logical OR of A0 and WR. WLB is Low when A0 and WR are both Low. The byte-write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common SRAMs.
Data Strobe Bus Interface Option
The Am186ED/EDLV microcontrollers provide an asynchronous bus interface that allows the use of 68Ktype peripherals. This implementation combines a DS data strobe signal (multiplexed with DEN) with an asynchronous ARDY ready input. When DS is asserted, the data and address signals are valid. A chip select signal, ARDY, DS, and other control signals (RD/WR) can control the interface of 68K-type external peripherals to the AD bus.
Programmable Bus Sizing
The Am186ED/EDLV microcontrollers allow programmability for data bus widths through fields in the Auxiliary Configuration Register (AUXCON) , as shown in Table 7. The USIZ bit in AUXCON is only configurable if the boot mode is 8-bit at reset. The width of the data access should not be modified while the processor is fetching instructions from the associated address space. Table 7. Programming the Bus Width of Am186ED/EDLV Microcontrollers
Space UCS AUXCON Field USIZ
DRAM INTERFACE
LCS I/O Other
D
Value 0 1 LSIZ 0 1 1 MSIZ 0 1 IOSIZ 0
Bus Width
R
Default Default Default
A
Comments
16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits
Dependent on boot option1
The Am186ED/EDLV microcontrollers support up to two banks of DRAM. The use of DRAM can significantly reduce the memory costs for applications using more than 64K of RAM. No performance is lost except for the slight overhead of periodically refreshing the DRAM. The lower bank of DRAM uses the LCS space. The upper bank of DRAM uses the UCS space. Either, neither, or both banks can be activated. When either bank is activated, the UCAS and LCAS are enabled, and the DRAM address multiplexing is enabled on the A19-A0 bus. When DRAM is activated, the corresponding memory bus size should be set to 16-bit. The use of 8-bit-wide DRAM is not supported. All refreshes to DRAM are 7 clocks long. The refreshes must be separately enabled in the RCU. The improved memory timing specifications of the Am186ED/EDLV microcontrollers allow for zero-waitstate operation using 50-ns DRAM at a 40-MHz clock speed. 60-ns DRAM requires one wait state at 40 MHz and zero wait states at 33 MHz and below. 70-ns DRAM requires two wait states at 40 MHz, one wait state at 33 MHz, and zero wait states at 25 MHz and below. This reduces overall system cost by enabling the use of commonly available memory speeds and taking advantage of DRAM's lower cost per bit over SRAM.
T F
Note: 1. UCS width on reset is determined by the S2/BTSEL pin. If UCS boots as a 16-bit space, it is not re-configurable to 8-bit.
Am186ED/EDLV Microcontrollers
37
PRELIMINARY
PERIPHERAL CONTROL BLOCK
The integrated peripherals of the Am186ED/EDLV microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte peripheral control block (PCB). The registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Table 8 shows a map of these registers.
Reading and Writing the PCB
Code written for the Am186ED/EDLV microcontrollers should perform all writes to the PCB registers as byte writes. These writes transfer 16 bits of data to the PCB register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner runs correctly on the Am186ED/EDLV microcontrollers with the PCB overlayed on either 8- or 16-bit address spaces. Unaligned reads and writes to the PCB result in unpredictable behavior. For a complete description of all the registers in the PCB, see the Am186ED/EDLV Microcontrollers User's Manual, order# 21335A.
D
38
R
A
T F
Am186ED/EDLV Microcontrollers
PRELIMINARY Table 8. Peripheral Control Block Register Map
Register Name Processor Control Registers: Peripheral control block relocation register Reset configuration register Processor release level register Auxiliary configuration register1 System configuration register1 Watchdog timer control register Enable RCU register (See note 2.) DMA Registers: DMA 1 control register DMA 1 transfer count register DMA 1 destination address high register DMA 1 destination address low register DMA 1 source address high register DMA 1 source address low register DMA 0 control register DMA 0 transfer count register DMA 0 destination address high register DMA 0 destination address low register DMA 0 source address high register DMA 0 source address low register Chip-Select Registers: PCS and MCS auxiliary register Peripheral chip-select register Low memory chip-select register Serial Port 0 Registers: Upper memory chip-select register1 DAh D8h D6h D4h D2h D0h CAh C8h C6h C4h C2h C0h
1 1
Register Name Timer 2 max count compare A register Timer 2 count register Timer 1 mode/control register Timer 1 max count compare B register Timer 1 max count compare A register Timer 1 count register Timer 0 mode/control register Timer 0 max count compare B register Timer 0 max count compare A register Timer 0 count register Interrupt Registers: Serial port 0 interrupt control register Serial port 1 interrupt control register INT4 interrupt control register INT3 control register INT2 control register INT1 control register INT0 control register
Offset 62h 60h 5Eh 5Ch 5Ah 58h 56h 54h 52h 50h 44h 42h 40h 3Eh 3Ch 3Ah 38h 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 26h 24h 22h 20h 18h 16h 14h 12h 10h
Offset FEh F6h F4h F2h F0h E6h E4h E2h
Clock prescaler register1
DMA1/INT6 interrupt control register DMA0/INT5 interrupt control register Timer interrupt control register Interrupt status register Interrupt request register
Midrange memory chip-select register
1
Serial port 0 baud rate divisor register Serial port 0 receive register Serial port 0 status register PIO Registers: PIO data 1 register PIO direction 1 register PIO mode 1 register PIO data 0 register PIO direction 0 register PIO mode 0 register Timer Registers: Timer 2 mode/control register Serial port 0 transmit register Serial port 0 control register
D
R
A8h
A6h A2h A0h 88h 86h 84h 82h 80h 7Ah 78h 76h 74h 72h 70h 66h
A4h
A
Notes:
Interrupt in-service register Interrupt mask register
T F
Interrupt priority mask register Interrupt poll status register Interrupt poll register End-of-interrupt register Interrupt vector register Serial Port 1 Registers: Serial port 1 baud rate divisor register Serial port 1 receive register Serial port 1 transmit register Serial port 1 status register Serial port 1 control register
All unused addresses are reserved and should not be accessed. 1. The register has been modified from the Am186ES/ Am188ES microcontrollers. 2. The previous Memory Partition Register (MDRAM) has been removed and its functionality replaced with the CAS-before-RAS refresh mode.
Am186ED/EDLV Microcontrollers
39
PRELIMINARY
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the Am186ED/EDLV microcontrollers includes a phaselocked loop (PLL) and a second programmable system clock output (CLKOUTB). the output of the amplifier and negatively affects the operation of the clock generator. Values for the loading on X1 and X2 must be chosen to provide the necessary phase shift and crystal operation. Selecting a Crystal When selecting a crystal, the load capacitance should always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: (C1 C2) CL = + CS (C1 + C2) where CS is the stray capacitance of the circuit. Placing the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance. This relationship is true for both fundamental and third-overtone operation. Finally, there is a relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (X2). Equal values of these loads tend to balance the poles of the inverting amplifier. The characteristics of the inverting amplifier set limits on the following parameters for crystals: ESR (Equivalent Series Resistance) ......60 max Drive Level ..............................................1 mW max
Phase-Locked Loop
In a traditional 80C186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. Because of the PLL on the Am186ED/EDLV microcontrollers, the internal clock generated by the Am186ED/EDLV microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45-55% (worst case) duty cycle intermediate system clock of the same frequency. This removes the need for an external 2x oscillator, reducing system cost. The PLL is reset during power-on reset by an on-chip power-on reset (POR) circuit.
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ED/EDLV microcontrollers is designed to function with a parallel resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency should be equal to the processor frequency. Do not replace a crystal with an LC or RC equivalent. The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (Figure 8). In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1). The external feedback network provides an additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback dampens
D
Crystal
R
A
T F
C1 X1 Crystal X2 C2 Note 1 200 pF
The recommended range of values for C1 and C2 are as follows: C1 ..................................................................15 pF 20% C2 ..................................................................22 pF 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design.
C1
C2
Am186ED/EDLV Microcontrollers
a. Inverting Amplifier Configuration
Note 1: Use for Third Overtone Mode XTAL Frequency L1 Value (Max) 20 MHz 12 H 20% 25 MHz 8.2 H 20% 33 MHz 4.7 H 20% 40 MHz 3.0 H 20%
b. Crystal Configuration
Figure 8.
Am186ED/EDLV Microcontrollers Oscillator Configurations
40
Am186ED/EDLV Microcontrollers
PRELIMINARY
External Source Clock
Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1), with the output (X2) not connected.
Initialization and Processor Reset
Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be held Low for 1 ms during power-up to ensure proper device initialization. RES forces the Am186ED/EDLV microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active. After RES becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h, with UCS asserted with three wait states. RES also sets some registers to predefined values and resets the watchdog timer.
System Clocks
The base system clock of AMD's original 80C186 and 80C188 microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and CLKOUTB operate at either the processor frequency or the PLL frequency. The output drivers for both clocks are individually programmable for disable. Figure 9 shows the organization of the clocks. The second clock output (CLKOUTB) allows one clock to run at the PLL frequency and the other clock to run at the power-save frequency. Individual drive enable bits allow selective enabling of just one or both of these clock outputs.
Reset Configuration Register
When the RES input is asserted Low, the contents of the address/data bus (AD15-AD0) are written into the reset configuration register. The system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. The processor does not drive the address/data bus during reset. For example, the reset configuration register could be used to provide the software with the position of a configuration switch in the system. Using weak external pullup and pulldown resistors on the address and data bus, the system can provide the microcontroller with a value corresponding to the position of the jumper during a reset.
Power-Save Operation
The power-save mode of the Am186ED/EDLV microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clock's next rising edge of t3.
Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. Software drivers must be aware of clock frequency. The power-save divisor should not be set to operate the processor core below 100 kHz.
X1, X2
D
PLL /2
R
A
Mux
T F
Processor Clock CAD Time Delay 6 ns CBD
PSEN
Mux
Power-Save Divisor /1 to /128
CAF CLKOUTA
CLKDIV2 Mux
CBF CLKOUTB
Mux
Note: For frequencies under 16 MHz, use PLL bypass.
Figure 9. Clock Organization
Am186ED/EDLV Microcontrollers
41
PRELIMINARY
CHIP-SELECT UNIT
The Am186ED/EDLV microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. The logic can be programmed to provide ready and wait-state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. The Am186ED/EDLV microcontrollers provide six chipselect outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space. The six memory chip selects can be used to address three memory ranges. Each peripheral chip select addresses a 256-byte block that is offset from a programmable base address. A write to a chip select register will enable the corresponding chip select logic even if the actual pin has another function (e.g., PIO). The ARDY signal on the Am186ED/EDLV microcontrollers is a true asynchronous ready signal. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period may be added.
Chip-Select Overlap
Although programming the various chip selects on the Am186ED/EDLV microcontrollers so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The one exception to this is PCS overlapping DRAM. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB can be programmed to addresses that overlap external chip-select signals only if those external chip selects are programmed to zero wait states with no external ready required.
Chip-Select Timing
The timing for the UCS and LCS outputs is modified from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced.
Ready and Wait-State Programming
The Am186ED/EDLV microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chipselect control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ignored. The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS, MCS3-MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3-PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, and one more wait state occurs followed by t4.
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When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register disables the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert.
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The MCS and PCS chip-select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs. It should be noted, however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are enabled (by a write to the MMCS and MPCS for the MCS chip selects, or by a write to the PACS and MPCS registers for the PCS chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects.
Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6- PCS5 is disabled when these signals are configured as address bits A2-A1. Failure to configure overlapping chip selects with the same ready and wait state requirements may cause
42
Am186ED/EDLV Microcontrollers
PRELIMINARY the processor to hang with the appearance of waiting for a ready signal. This behavior may occur even in a system in which ready is always asserted (ARDY or SRDY tied High). Configuring PCS in I/O space with LCS or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. The PCS can overlap DRAM blocks with different wait states and without external or internal bus contention. The RAS will assert along with the appropriate PCS. The UCAS and LCAS will not assert, preventing the DRAM from writing erroneously or driving the data bus during a read. The PCS must have the same or higher number of wait states than the DRAM. The PCS bus width will be determined by the LSIZ or USIZ bus widths. This will make a 1785-byte block of the DRAM inaccessible. In its place, the peripherals associated with the PCS can be accessed. This is especially useful when the entire memory space is used with two banks of DRAM or a bank of DRAM and a 512K Flash.
Low Memory Chip Select
The Am186ED/EDLV microcontrollers provide an LCS chip select for lower memory. The AUXCON register can be used to configure LCS for 8-bit or 16-bit accesses. Since the interrupt vector table is located at the bottom of memory starting at 00000h, the LCS pin is usually used to control data memory. The LCS pin is not active on reset. The LCS signal is multiplexed with the RAS0 signal when the DRAM mode is enabled in the LMCS register.
Midrange Memory Chip Selects
The Am186ED/EDLV microcontrollers provide four chip selects, MCS3-MCS0, for use in a user-locatable memory block. With some exceptions, the base address of the memory block can be located anywhere within the 1-Mbyte memory address space. The areas associated with the UCS and LCS chip selects are excluded. If they are mapped to memory, the address range of the peripheral chip selects, PCS6, PCS5, and PCS3-PCS0, are also excluded. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O space. MCS0 can be configured to be asserted for the entire MCS range. When configured in this mode, the MCS3- MCS1 pins can be used as PIOs or DRAM control signals. The AUXCON register can be used to configure MCS for 8-bit or 16-bit accesses. The bus width of the MCS range is determined by the width of the non-UCS/nonLCS memory range. Unlike the UCS and LCS chip selects, the MCS outputs assert with the same timing as the multiplexed AD address bus.
Upper Memory Chip Select
The Am186ED/EDLV microcontrollers provide a UCS chip select for the top of memory. On reset the Am186ED/EDLV microcontrollers begin fetching and executing instructions at memory location FFFF0h. Therefore, upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted. The UCS memory range always ends at FFFFFh. The UCS lower boundary is programmable. The bus width associated with UCS is determined on reset by the S2/BTSEL. If S2/BTSEL is pulled High or left floating, an internal pullup sets the boot mode option to 16-bit. If S2/BTSEL is pulled resistively Low during reset, the boot mode option is for 8-bit. The status of the S2/BTSEL pin is latched on the rising edge of reset. If 8-bit mode is selected, the width of the memory region associated with UCS can be changed in the AUXCON register. If UCS boots as a 16-bit space, it is not re-configurable to 8-bit. This allows for cheaper 8bit-wide memory to be used for booting the Am186ED/ EDLV microcontrollers, while speed-critical code and data can be executed from 16-bit-wide lower memory. Eight-bit or 16-bit-wide peripherals can be used in the memory area between LCS and UCS or in the I/O space. The entire memory map can be set to 16-bit or 8-bit or mixed between 8-bit and 16-bit based on the USIZ, LSIZ, MSIZ, and IOSIZ bits in the AUXCON register.
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Activating either bank of DRAM will change the MCS1 and MCS2 functionality to UCAS and LCAS. Activating the upper DRAM bank will change the MCS3 functionality to RAS1. It is recommended that when either bank of DRAM is activated, either MCS0 be configured to assert for the entire MCS range or that MCS space be unused. If the lower bank of DRAM is activated, but not the upper bank of DRAM, MCS3 can still be used as a chip select or PIO. The MCS2 and MCS1 portion of the middle chip select address space will not have a chip select signal asserted, but the wait states will still be valid.
Peripheral Chip Selects
The Am186ED/EDLV microcontrollers provide six chip selects, PCS6-PCS5 and PCS3-PCS0, for use within a user-configured memory or I/O block. PCS4 is not available on the Am186ED/EDLV microcontrollers. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and
Am186ED/EDLV Microcontrollers
43
PRELIMINARY MCS chip selects, or they can be configured to access the 64-Kbyte I/O space. The PCS pins are not active on reset. PCS6-PCS5 can be programmed for zero to three wait states. PCS3- PCS0 can be programmed for four additional wait-state values: 5, 7, 9, and 15. The AUXCON register can be used to configure PCS for 8-bit or 16-bit accesses. The bus width of the PCS range is determined by the width of the non-UCS/nonLCS memory range or by the width of the I/O area. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186/188 microcontrollers. The PCS allows for overlap in memory space with the DRAM (RAS0, RAS1) space. Overlap of the PCS with LCS, MCS, or UCS in a non-DRAM mode is not recommended. If overlap of the PCS with MCS, LCS, or UCS occurs, the same number of wait states and external ready must be used. If overlap of PCS with DRAM space occurs, the DRAM controller will assert RAS and stop the CAS signal from asserting. This will not modify the contents of the DRAM and the access will continue as a normal PCS access. When overlapping the PCS with DRAM, the number of wait states can be different for PCS space. PCS wait states must be greater than or equal to DRAM wait states. The ready and wait states will be determined by the PCS programming in the MPCS and PACS registers. PCS space should not contain the address FFFFFh, which is the address used for a refresh cycle. The AD15-AD0 bus will drive FFFFh during a refresh cycle for the address portion of cycle.
INTERRUPT CONTROL UNIT
The Am186ED/EDLV microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are up to eight external interrupt sources on the Am186ED/EDLV microcontrollers--seven maskable interrupt pins and one nonmaskable interrupt (NMI) pin. In addition, there are eight internal interrupt sources (three timers, two DMA channels, two asynchronous serial ports, and the Watchdog Timer NMI) that are not connected to external pins. INT5 and INT6 are multiplexed with DRQ0 and DRQ1. These two interrupts are available if the associated DMA is not enabled or is being used with internal synchronization. The Am186ED/EDLV microcontrollers provide up to six interrupt sources not present on the 80C186 and 80C188 microcontrollers. There are up to three additional external interrupt pins--INT4, INT5, and INT6. These pins operate much like the INT3-INT0 interrupt pins on the 80C186 and 80C188 microcontrollers. There are also two internal interrupts from the serial ports and the watchdog timer can generate interrupts.
REFRESH CONTROL UNIT
The refresh control unit (RCU) automatically generates refresh bus cycles when enabled. After a programmable period of time, the RCU generates a CAS-beforeRAS refresh bus cycle. The RCU should not be enabled if at least one bank of DRAM is not enabled. All refreshes will be 7 clocks, no matter how the DRAM wait states are programmed. During a refresh cycle, the A19-A0 bus is undefined; the AD15-AD0 bus is driven with all 1s (FFFFh). The PCS and MCS chip selects are decoded by the processor using a 20-bit version of the AD bus. The highest four bits of this internal bus are not available externally; however, internally these bits are set to all 1s during a refresh cycle, resulting in the 20-bit address FFFFFh. For this reason, the MCS and PCS chip selects should not contain the address FFFFFh while DRAM is enabled.
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INT5 and INT6 are multiplexed with the DMA request signals, DRQ0 and DRQ1. If a DMA channel is not enabled, or if it is not using external synchronization, then the associated pin can be used as an external interrupt. INT5 and INT6 can also be used in conjunction with the DMA terminal count interrupts.
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The seven maskable interrupt request pins can be used as direct interrupt requests. INT4-INT0 can be either edge-triggered or level-triggered. INT6 and INT5 are edge-triggered only. In addition, INT0 and INT1 can be configured in cascade mode for use with an external 82C59A-compatible interrupt controller. When INT0 is configured in cascade mode, the INT2 pin is automatically configured in its INTA0 function. When INT1 is configured in cascade mode, the INT3 pin is automatically configured in its INTA1 function. An external interrupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. INT6-INT4 are not available in slave mode. Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines (ISRs) may re-enable interrupts by setting the IF flag. This allows interrupts of greater or equal priority to interrupt the currently executing ISR. Interrupts from the same source are disabled as long as the corresponding bit in the interrupt in-service register is set. INT1 and INT0 provide a special bit to enable special fully nested mode. When configured in special fully nested mode, the interrupt source may generate a new interrupt regardless of the setting of the in-service bit.
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Am186ED/EDLV Microcontrollers
PRELIMINARY
TIMER CONTROL UNIT
There are three 16-bit programmable timers and a watchdog timer on the Am186ED/EDLV microcontrollers. Timer 0 and timer 1 are connected to four external pins (each one has an input and an output). These two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. When pulse width demodulation is enabled, timer 0 and timer 1 are used to measure the width of the High and Low pulses on the PWD pin. (See the Pulse Width Demodulation section on page 45.) Timer 2 is not connected to any external pins. It can be used for real-time coding and time-delay applications. It can also be used as a prescaler to timers 0 and 1 or to synchronize DMA transfers. The programmable timers are controlled by eleven 16bit registers in the peripheral control block. A timer's timer-count register contains the current value of that timer. The timer-count register can be read or written with a value at any time, whether the timer is running or not. The microcontroller increments the value of the timer-count register each time a timer event occurs. Each timer also has a maximum-count register that defines the maximum value the timer can reach. When the timer reaches the maximum value, it resets to 0 during the same clock cycle. The value in the maximum-count register is never stored in the timer-count register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low for one clock cycle after the maximum value is reached. If the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform depends on the values in the maximumcount registers. Each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter of the internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer circuitry, the timer output can take up to six clock cycles to respond to the clock or gate input.
after reset. It can only be modified a single time by a keyed sequence of writes to the watchdog timer control register (WDTCON) following reset. This single write can either disable the timer or modify the timeout period and the action taken upon timeout. A keyed sequence is also required to reset the current WDT count. This behavior ensures that randomly executing code will not prevent a WDT event from occurring. The WDT supports up to a 1.67-second timeout period in a 40-MHz system. After reset, the WDT is enabled and the timeout period is set to its maximum value. The WDT can be configured to cause either an NMI interrupt or a system reset upon timeout. If the WDT is configured for NMI, the NMIFLAG in the WDTCON register is set when the NMI is generated. The NMI interrupt service routine (ISR) should examine this flag to determine if the interrupt was generated by the WDT or by an external source. If the NMIFLAG is set, the ISR should clear the flag by writing the correct keyed sequence to the WDTCON register. If the NMIFLAG is set when a second WDT timeout occurs, a WDT system reset is generated rather than a second NMI event. When the processor takes a WDT reset, either due to a single WDT event with the WDT configured to generate resets or due to a WDT event with the NMIFLAG set, the RSTFLAG in the WDTCON register is set. This allows system initialization code to differentiate between a hardware reset and a WDT reset and take appropriate action. The RSTFLAG is cleared when the WDTCON register is read or written. The processor does not resample external pins during a WDT reset. This means that the clocking, the reset configuration register, and any other features that are user-selectable during reset do not change when a WDT system reset occurs. All other activities are identical to those of a normal system reset.
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Note: The Watchdog Timer (WDT) is active after reset.
PULSE WIDTH DEMODULATION
For many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its High and Low phases. The Am186ED/EDLV microcontrollers provide a pulse-width demodulation (PWD) option to fulfill this need. The PWD bit in the System Configuration Register (SYSCON) enables the PWD option. Analog-to-digital conversion is not supported. In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are configured internal to the microcontroller to support the detection of rising and falling edges on the PWD input pin (INT2/INTA0/PWD) and to enable either timer 0 when the signal is High or timer 1 when the signal is Low. The INT4, TMRIN0, and TMRIN1 pins are not used in PWD mode and so are available for use as PIOs.
Watchdog Timer
The Am186ED/EDLV microcontrollers provide a true watchdog timer function. The Watchdog Timer (WDT) can be used to regain control of the system when software fails to respond as expected. The WDT is active
Am186ED/EDLV Microcontrollers
45
PRELIMINARY The following diagram shows the behavior of a system for a typical waveform. the event of a simultaneous DMA request or if there is a need to interrupt transfers on the other channel.
DMA Operation
Each channel has six registers in the peripheral control block that define specific channel operations. The DMA registers consist of a 20-bit source address (two registers), a 20-bit destination address (two registers), a 16bit transfer count register, and a 16-bit control register. The DMA Transfer Count Register (DTC) specifies the number of DMA transfers to be performed. Up to 64K of byte or word transfers can be performed with automatic termination. The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation. Table 9. Am186ED/EDLV Microcontrollers Maximum DMA Transfer Rates
INT2
INT4
INT2 Ints generated TMR1 enabled TMR0 enabled
The interrupt service routine (ISR) for the INT2 and INT4 interrupts should examine the current count of the associated timer, timer 1 for INT2, and timer 0 for INT4, in order to determine the pulse width. The ISR should then reset the timer count register in preparation for the next pulse. Since the timers count at one quarter of the processor clock rate, this determines the maximum resolution that can be obtained. Further, in applications where the pulse width may be short, it may be necessary to poll the INT2 and INT4 request bits in the interrupt request register in order to avoid the overhead involved in taking and returning from an interrupt. Overflow conditions, where the pulse width is greater than the maximum count of the timer, can be detected by monitoring the Maximum Count (MC) bit in the associated timer or by setting the INT bit to enable timer interrupt requests.
Type of Synchronization Selected Unsynchronized
DIRECT MEMORY ACCESS
Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit shown in Figure 10, provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory to memory or I/O to I/O). Table 9 shows maximum DMA transfer rates. The DMA channels can be directly connected to the asynchronous serial ports. DMA and serial port transfer is accomplished by programming the DMA controller to perform transfers between a data source in memory or I/O space and a serial port transmit or receive register. The two DMA channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. Either bytes or words can be transferred to or from even or odd addresses. However, word DMA transfers to or from memory configured for 8-bit accesses are not supported. Only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. Each channel accepts a DMA request from one of four sources: the channel request pin (DRQ1-DRQ0), Timer 2, a serial port, or the system software. The channels can be programmed with different priorities in 46
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Source Synchronized
Destination Synchronized (CPU needs bus) Destination Synch (CPU does not need bus)
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40 MHz 10 33 MHz 8.25 25 MHz 6.25 10 8.25 5.5 6.6 6.25 6.6 8 4.16 5
Maximum DMA Transfer Rate (Mbytes) 20 MHz 5 5 3.3 4
Am186ED/EDLV Microcontrollers
PRELIMINARY
20-bit Adder/Subtractor
Adder Control Logic
Timer Request DRQ1/Serial Port Request Selection Logic
20
DRQ0/Serial Port
Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 DMA Control Logic
Interrupt Request
Channel Control Register 1 Channel Control Register 0 20 16
Internal Address/Data Bus
Figure 10.
DMA Unit Block Diagram
DMA Channel Control Registers
Each DMA control register determines the mode of operation for the particular DMA channel. The DMA control registers specify the following: n The mode of synchronization n Whether bytes or words are transferred
n Whether an interrupt is generated after the last transfer n Whether the DRQ pins are configured as INT pins n Whether DMA activity ceases after a programmed number of DMA cycles n The relative priority of the DMA channel with respect to the other DMA channel n Whether the source address is incremented, decremented, or maintained constant after each transfer n Whether the source address addresses memory or I/O space n Whether the destination address is incremented, decremented, or maintained constant after transfers n Whether the destination address addresses memory or I/O space
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DMA Priority
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The DMA channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles except between locked memory accesses or word accesses to odd memory locations. However, an external bus hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows the CPU to respond quickly to the NMI request.
ASYNCHRONOUS SERIAL PORTS
The Am186ED/EDLV microcontrollers provide two independent asynchronous serial ports. These ports provide full-duplex, bidirectional data transfer using several industry-standard communications protocols. The serial ports can be used as sources or destinations of DMA transfers.
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PRELIMINARY The asynchronous serial ports support the following features: n Full-duplex operation n Direct memory access (DMA) from the serial ports n 7-bit, 8-bit, or 9-bit data transfers n Odd, even, or no parity n One stop bit n Long or short break character recognition n Error detection -- Parity errors -- Framing errors -- Overrun errors -- Break character recognition n Hardware handshaking with the following selectable control signals: -- Clear-to-send (CTS) -- Enable-receiver-request (ENRX) -- Ready-to-send (RTS) -- Ready-to-receive (RTR) n DMA to and from the serial ports n Separate maskable interrupts for each port n Multidrop protocol (9-bit) support n Independent baud rate generators n Maximum baud rate of 1/16th of the CPU clock n Double-buffered transmit and receive n Programmable interrupt generation for transmit, receive, and/or error detection
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ED/EDLV microcontrollers that are available as user-programmable I/O signals. Table 2 on page 29 and Table 3 on page 29 list the PIO pins. Each of these pins can be used as a userprogrammable input or output signal if the normal shared function is not needed. If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect the level on the pin. A PIO signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 on page 29 and Table 3 on page 29 lists the defaults for the PIOs. The system initialization code must reconfigure the PIOs as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Note that emulators use A19, A18, A17, S6, and UZI. In environments where an emulator is needed, these pins must be configured for normal function--not as PIOs.
DMA Transfers through the Serial Port
The DMA channels can be directly connected to the asynchronous serial ports. DMA and serial port transfer is accomplished by programming the DMA controller to perform transfers between a memory or I/O space and a serial port transmit or receive register. The two DMA channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. See the DMA Control register descriptions in the Am186ED/ EDLV Microcontrollers User's Manual, order# 21335A for more information.
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If the AD15-AD0 bus override is enabled on power-on reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN is held Low during power-on reset, the AD15-AD0 bus override is enabled.
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When the PCS or MCS are used as PIO inputs (only) and the bus is arbitrated, an internal pullup of ~10 kohms is activated, even if the pullup option for the PIO is not selected.
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Am186ED/EDLV Microcontrollers
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage temperature Am186ED........................................ -65C to +125C Am186EDLV.................................... -65C to +125C Voltage on any pin with respect to ground Am186ED................................... -0.5 V to Vcc +0.5 V Am186EDLV............................... -0.5 V to Vcc +0.5 V
OPERATING RANGES
Am186ED Microcontroller Commercial (TC) .................................0C to +100C Industrial* (TA)...................................-40C to +85C Supply voltage (VCC) .................................5 V 10% Am186EDLV Microcontroller Commercial (TA) ................................... 0C to +70C VCC up to 25 MHz................................. 3.3 V 0.3 V Where: TC = case temperature TA = ambient temperature
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
*Industrial versions of Am186ED microcontrollers are available in 20 and 25 MHz operating frequencies only.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES
Symbol Parameter Description Input Low Voltage (Except X1) Clock Input Low Voltage (X1) Input High Voltage (Except RES and X1) Input High Voltage (RES) Clock Input High Voltage (X1) Output Low Voltage Am186ED VOL Am186EDLV Output High Voltage(a) VOH Am186ED Am186EDLV ICC ILI ILO VCLO VCHO IOL = 2.5 mA (S2-S0) IOL = 2.0 mA (others) Test Conditions
VIL VIL1 VIH VIH 1 VIH 2
Power Supply Current @ 0C
Input Leakage Current @ 0.5 MHz Clock Output Low
Output Leakage Current @ 0.5 MHz Clock Output High
Notes: a The LCS/ONCE0/RAS0 and UCS/ONCE1 pins have weak internal pullup resistors. Loading the LCS/ONCE0/RAS0 and UCS/ONCE1 pins in excess of IOH = -200 A during reset can cause the device to go into ONCE mode. b c Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open but held High or Low. Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode.
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IOH = -2.4 mA @ 2.4 V
IOH = -200 A @ VCC -0.5 IOH = -200 A @ VCC -0.5 = 5.5 V (b) VCC
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(c)
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Preliminary Min Max 0.8 -0.5 2.0 0.2VCC -0.3 VCC +0.5 VCC +0.5 VCC +0.5 0.45 0.45 -0.5 2.4 VCC -0.8 2.4 VCC -0.5 VCC -0.5 VCC +0.5 VCC VCC 5.9 4.0 10 10 0.45 VCC -0.5
Unit V V V V V V V
V V V mA/MHz A A V V
VCC = 3.6 V (b) 0.45 VVOUT VCC
0.45 VVIN VCC ICLO = 4.0 mA ICHO = -500 A
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PRELIMINARY
CAPACITANCE
Preliminary Symbol CIN CIO Parameter Description Input Capacitance Output or I/O Capacitance Test Conditions @ 1 MHz @ 1 MHz Min Max 10 20 Unit pF pF
Note: Capacitance limits are guaranteed by characterization.
POWER SUPPLY CURRENT
For the following typical system specification shown in Figure 11, ICC has been measured at 4.0 mA per MHz of system clock. For the following typical system specification shown in Figure 12, I CC has been measured at 5.9 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with nominal voltage and maximum case temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Typical current in Figure 11 is given by: ICC = 4.0 mA freq(MHz) Typical current in Figure 12 is given by: ICC = 5.9 mA freq(MHz) Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: n No DC loads on the output buffers n AD bus set to data only n PIOs are disabled n Output capacitive load set to 35 pF Table 10 shows the variables that are used to calculate t he t y p i c a l p o we r c o n s um p t i o n v a l u e f o r t h e Am186EDLV microcontroller. Table 10. Typical Power Consumption Calculation for the Am186EDLV Microcontroller
MHz ICC Volts / 1000 = P MHz 20 25 Typical ICC 4.0 4.0
140
n Timer, serial port, refresh, and DMA are enabled
D
ICC (mA)
R
10
A
ICC (mA)
25 MHz 20 MHz 20 30
120
100 80 60
T F
Volts 3.6 3.6
20 MHz 10 20
Typical Power in Watts 0.288 0.360
25 MHz
40 20 0 30
Clock Frequency (MHz)
Figure 11. Typical Icc Versus Frequency for Am186EDLV Microcontroller
280 240 33 MHz 40 MHz
200 160 120 80 40 0
40
50
Clock Frequency (MHz)
Figure 12. Typical Icc Versus Frequency for Am186ED Microcontroller
50
Am186ED/EDLV Microcontrollers
PRELIMINARY
THERMAL CHARACTERISTICS TQFP Package
The Am186ED microcontroller is specified for operation with case temperature ranges from 0C to +100C for a commercial device. Case temperature is measured at the top center of the package as shown in Figure 13. The various temperatures and thermal resistances can be determined using the equations in Figure 14 with information given in Table 11. The total thermal resistance is JA; JA is the sum of JC, the internal thermal resistance of the assembly, and CA, the case to ambient thermal resistance.
The variable P is power in watts. Power supply current (ICC) is in mA per MHz of clock frequency. JA TC JC CA
JA = JC + CA Figure 13. Thermal Resistance(C/Watt)
JA = JC + CA P=ICC freq (MHz) VCC TJ =TC +( PJC ) TJ =TA + ( PJA ) TC =TJ -( PJC ) TC =TA +( PCA ) TA =TJ -( PJA ) TA =TC -( PCA ) Figure 14.
Thermal Characteristics Equations
Table 11. Thermal Characteristics (C/Watt)
Package/Board PQFP/2-Layer
D
TQFP/2-Layer
R
Airflow (Linear Feet per Minute) 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm
A
JA 45 39 35 33 56 46 40 38 23 21 19 17 30 28 26 24
T F
CA 38 32 28 26 46 36 30 28 18 16 14 12 24 22 20 18
JC 7 7 7 7 10 10 10 10 5 5 5 5 6 6 6 6
PQFP/4-Layer to 6-Layer
TQFP/4-Layer to 6-Layer
0 fpm 200 fpm 400 fpm 600 fpm
Am186ED/EDLV Microcontrollers
51
PRELIMINARY
Typical Ambient Temperatures
The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186ED microcontroller is a case temperature TC of 0 to 100 degrees Centigrade. TC is measured at the top center of the package. An increase in the ambient temperature causes a proportional increase in TC. Microcontrollers up to 40 MHz are specified as 5.0 V plus or minus 10%. Therefore, 5.0 V is used for calculating typical power consumption up to 40 MHz. Typical power supply current (ICC) in normal usage is estimated at 5.9 mA per MHz of microcontroller clock rate. Typical power consumption (watts) = (5.9 mA/MHz) times microcontroller clock rate times VCC divided by 1000. Table 12 shows the variables that are used to calculate the typical power consumption value for each version of the Am186ED microcontroller.
Table 13. Junction Temperature Calculation
Speed/ Pkg/ Board 40/P2 40/T2 40/P4-6 40/T4-6 33/P2 33/T2 33/P4-6 33/T4-6 25/P2 25/T2 25/P4-6 25/T4-6 20/P2 20/T2 20/P4-6 20/T4-6 TJ = TC + (P JC) TJ(C) 108.3 111.8 105.9 107.1 106.8 109.7 104.9 105.8 105.2 107.4 103.7 104.4 105.9 104.1 TC 100 100 100 100 100 100 100 100 100 100 100 100 P 1.2 1.2 1.2 1.2 1.0 1.0 1.0 1.0 0.7 0.7 0.7 0.7 JC 7 10 5 6 7 10 5 6 7 10 5 6 7 10 5 6
103.0 103.5
Table 12.
Typical Power Consumption Calculation
Typical Power (P) in Watts 5.0 5.0 5.0 5.0 1.2 1.0 0.7 0.6
P = MHz ICC VCC/1000 MHz 40 33 25 20 Typical ICC 5.9 5.9 5.9 5.9 Volts
Thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. A safe operating range for the device can be calculated using the formulas from Figure 14 and the variables in Table 11. By using the maximum case rating T C , the typical power consumption value from Table 12, and JC from Table 11, the junction temperature TJ can be calculated by using the following formula from Figure 14. TJ = TC + (P JC) Table 13 shows TJ values for the various versions of the Am186ED microcontroller. The column titled Speed/Pkg/Board in Table 13 indicates the clock speed in MHz, the type of package (P for PQFP and T for TQFP), and the type of board (2 for 2-layer and 4-6 for 4-layer to 6-layer).
D
R
A
By using T J from Table 13, the typical power consumption value from Table 12, and a JA value from Table 11, the typical ambient temperature TA can be calculated using the following formula from Figure 14: TA = TJ - (P JA)
T F
100 0.6 100 0.6 100 0.6 100 0.6
For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows: TA = 108.3 - (1.2 45) TA = 55.2
In this calculation, TJ comes from Table 13, P comes from Table 12, and JA comes from Table 11. See Table 14. TA for a 33-MHz TQFP design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: TA = 105.8 - (1.0 28) TA = 78.6 See Table 17 for the result of this calculation. Table 14 through Table 17 and Figure 15 through F i g u r e 1 8 s h o w TA b a s e d o n t h e p r e c e d i n g assumptions and calculations for a range of JA values with airflow from 0 linear feet per minute to 600 linear feet per minute.
52
Am186ED/EDLV Microcontrollers
PRELIMINARY Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 15 graphically illustrates the typical temperatures in Table 14. Table 14. Typical Ambient Temperatures (C) for PQFP with a 2-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.2 1.0 0.7 0.6 0 fpm 55.2 63.0 72.0 77.6 200 fpm 62.2 68.8 76.4 81.1 400 fpm 67.0 72.7 79.4 83.5 600 fpm 69.3 74.7 80.8 84.7
90
Typical Ambient Temperature (Degrees C)
s 80 s s x x
x 70
I I
q
I
60 q 50
q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
D
40
0 fpm
R
A
T F
s x
I
q
200 fpm
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Am186ED/EDLV Microcontrollers
53
PRELIMINARY Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 16 graphically illustrates the typical temperatures in Table 15. Table 15. Typical Ambient Temperatures (C) for TQFP with a 2-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.2 1.0 0.7 0.6 0 fpm 45.7 55.2 66.1 72.9 200 fpm 57.5 65.0 73.5 78.8 400 fpm 64.6 70.8 77.9 82.3 600 fpm 67.0 72.7 79.4 83.5
85 s Typical Ambient Temperature (Degrees C) s 75 s x x
s x
I
65 x
I
q
q 55
I
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
45
q
D
35
0 fpm
R
A
T F
I
q
600 fpm
200 fpm
400 fpm
Airflow (Linear Feet Per Minute)
Figure 16.
Typical Ambient Temperatures for TQFP with a 2-Layer Board
54
Am186ED/EDLV Microcontrollers
PRELIMINARY Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 17 graphically illustrates the typical temperatures in Table 16. Table 16. Typical Ambient Temperatures (C) for PQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.2 1.0 0.7 0.6 0 fpm 78.8 82.5 86.7 89.4 200 fpm 81.1 84.4 88.2 90.6 400 fpm 83.5 86.4 89.7 91.7 600 fpm 85.8 88.3 91.2 92.9
95 s Typical Ambient Temperature (Degrees C) s 90 s s x x 85 x
I I
q
I
q 80 q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
75
Figure 17.
D
70
0 fpm
R
A
T F
x
I
q
200 fpm
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Am186ED/EDLV Microcontrollers
55
PRELIMINARY Table 17 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 18 graphically illustrates the typical temperatures in Table 17. Table 17. Typical Ambient Temperatures (C) for TQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.2 1.0 0.7 0.6 0 fpm 71.7 76.6 82.3 85.8 200 fpm 74.0 78.6 83.8 87.0 400 fpm 76.4 80.5 85.3 88.2 600 fpm 78.8 82.5 86.7 89.4
90 s Typical Ambient Temperature (Degrees C) s s 85 x x 80
s
x
I I I
75 q q 70
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
Figure 18. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
D
65
0 fpm
R
A
q
T F
x
I
q
200 fpm
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
56
Am186ED/EDLV Microcontrollers
PRELIMINARY
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. In t h e s w i tc h i n g pa r a m e te r de s c r i p t i on s , t h e multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus.
Key to Switching Waveforms
WAVEFORM INPUT Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUT Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown
D
R
Invalid
A
Center Line is HighImpedance Off State Invalid
T F
Am186ED/EDLV Microcontrollers
57
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols
Parameter Symbol tARYCH tARYCHL tARYHDSH(a) tARYHDV
(a)
No. 49 51 95 89 52 96 87 14 12 66 65 24 45 68 104 101 38 44 67 18 22 64 63 8 9 11 3 ARDY Inactive Holding Time ARDY High to DS High ARDY Assert to Data Valid ARDY Setup Time ARDY Low to DS High
Description ARDY Resolution Transition Setup Time
tARYLCL tARYLDSH(a) tAVBL tAVCH tAVLL tAVRL tAVWL tAZRL tCH1CH2 tCHAV tCHCA tCHCAV tCHCK tCHCL tCHCSV tCHCSX tCHCTV tCHCV tCHCZ tCHDX tCHLH tCHLL tCHRA tCHSV tCICOA tCICOB tCHRX tCKHL tCKIN tCKLH
A Address Valid to WHB, WLB Low AD Address Valid to Clock High AD Address Valid to ALE Low A Address Valid to RD Low A Address Valid to WR Low AD Address Float to RD Active CLKOUTA Rise Time CLKOUTA High to A Address Valid CLKOUTA High to CAS Active X1 High Time CLKOUTA High Time CLKOUTA High to LCS/UCS Valid MCS/PCS Inactive Delay Control Active Delay 2
CLKOUTA Low to Column Address Valid
Command Lines Valid Delay (after Float) Command Lines Float Delay Status Hold Time ALE Active Delay
106 69 70 39 36 40 46 50 5 6 15 43 37 42
tCL2CL1 tCLARX tCLAV tCLAX tCLAZ tCLCH tCLCK tCLCL
D
103
R
ALE Inactive Delay
CLKOUTA High to RAS Active Status Active Delay X1 to CLKOUTA Skew X1 to CLKOUTB Skew
A
T F
CLKOUTA High to RAS Inactive X1 Fall Time X1 Period X1 Rise Time CLKOUTA Fall Time ARDY Active Hold Time AD Address Valid Delay and BHE Address Hold AD Address Float Delay CLKOUTA Low Time X1 Low Time CLKOUTA Period
58
Am186ED/EDLV Microcontrollers
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol tCLCSV tCLCX tCLRX tCLDOX tCLDV tCLDX tCLHAV tCLRA tCLRH tCLRL tCLSH tCLSRY tCLTMV tCOAOB(a) tCSHARYL(a) tCVCTV tCVCTX tCVDEX tCXCSX tDSHDIR(a) tDSHDIW tDSHDX(a) tDSHLH tDSLDD(a) tDSLDV(a) tDVCL tDVDSL(a) tDXDL tHVCL No. 16 105 107 30 7 2 62 102 27 25 4 48 55 83 88 20 31 21 17 92 98 93 41 90 91 1 97 19 58 53 54 23 10 13 61 99 110 111 57 29 59 94 28 MCS/PCS Active Delay CLKOUTA Low to CAS Inactive CLKOUTA Low to RAS Inactive Data Hold Time Data Valid Delay Data in Hold HLDA Valid Delay CLKOUTA Low to RAS Active RD Inactive Delay RD Active Delay Status Inactive Delay SRDY Transition Hold Time Timer Output Delay CLKOUTA to CLKOUTB Skew Chip Select to ARDY Low Control Active Delay 1 Control Inactive Delay DEN Inactive Delay DS High to Data Invalid--Read DS High to Data Invalid--Write DS Inactive to ALE Inactive DS Low to Data Driven DS Low to Data Valid Data in Setup Data Valid to DS Low HOLD Setup Peripheral Setup Time DRQ Setup Time ALE High to Address Valid ALE Width AD Address Hold from ALE Inactive Maximum PLL Lock Time PCS Active to ALE Inactive RAS To Column Address Delay Time with 0 Wait States RAS to Column Address Delay Time with 1 or More Wait States RES Setup Time RD Inactive to AD Address Active RD High to Data Hold on AD Bus RD High to Data Bus Turn-off Time RD Inactive to ALE High Description
MCS/PCS Hold from Command Inactive
DS High to Data Bus Turn-off Time
tINVCH tINVCL tLHAV tLHLL tLLAX
tLOCK tPLAL
D
(a)
R
A
T F
DEN Inactive to DT/R Low
tRD0W tRD1W tRESIN tRHAV tRHDX tRHDZ tRHLH
Am186ED/EDLV Microcontrollers
59
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol tRLRH tRP0W tRP1W tSRYCL tWHDEX tWHDX tWHLH tWLWH No. 26 108 109 47 35 34 33 32 RD Pulse Width RAS Inactive Pulse Width (0 Wait States) RAS Inactive Pulse Width (1 Wait State) SRDY Transition Setup Time WR Inactive to DEN Inactive Data Hold after WR WR Inactive to ALE High WR Pulse Width Description
Note: a Specs 83 and 88-97 are defined but not used at this time. Additionally, the following parameters are not defined nor used at this time: 56, 60, and 71-78.
D
60
R
A
T F
Am186ED/EDLV Microcontrollers
PRELIMINARY
Numerical Key to Switching Parameter Symbols
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Parameter Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tAZRL tCLRL tRLRH tCLRH Data in Setup Data in Hold Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low AD Address Hold from ALE Inactive AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Inactive Delay DEN Inactive to DT/R Low Control Active Delay 1 DEN Inactive Delay Control Active Delay 2 Description
MCS/PCS Hold from Command Inactive
ALE High to Address Valid
D
tRHLH tRHAV
tCLDOX tCVCTX tWLWH tWHLH tWHDX tCKIN tCLCK tCHCK tCKHL tCKLH tDSHLH tCLCL
R
AD Address Float to RD Active RD Active Delay RD Pulse Width
RD Inactive Delay
A
T F
RD Inactive to ALE High RD Inactive to AD Address Active Data Hold Time Control Inactive Delay WR Pulse Width WR Inactive to ALE High Data Hold after WR WR Inactive to DEN Inactive X1 Period X1 Low Time X1 High Time X1 Fall Time X1 Rise Time DS Inactive to ALE Inactive CLKOUTA Period
tWHDEX
Am186ED/EDLV Microcontrollers
61
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
No. 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 61 62 63 64 65 66 67 68 69 70 83(a) 87 88(a) 89(a) 90(a) 91(a) 92(a) 93(a) Parameter Symbol tCLCH tCHCL tCH1CH2 tCL2CL1 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV tRESIN tHVCL tRHDX tLOCK tCLHAV tCHCZ tCHCV tAVWL tAVRL tCHCSV tCHAV tCICOA tCICOB tCOAOB CLKOUTA Low Time CLKOUTA High Time CLKOUTA Rise Time CLKOUTA Fall Time SRDY Transition Setup Time SRDY Transition Hold Time ARDY Resolution Transition Setup Time ARDY Active Hold Time ARDY Inactive Holding Time ARDY Setup Time Peripheral Setup Time DRQ Setup Time Timer Output Delay RES Setup Time HOLD Setup RD High to Data Hold on AD Bus Maximum PLL Lock Time HLDA Valid Delay Command Lines Float Delay A Address Valid to WR Low A Address Valid to RD Low Description
Command Lines Valid Delay (after Float)
CLKOUTA High to LCS/UCS Valid
D
tAVBL
tCSHARYL tARYHDV tDSLDD tDSLDV
R
CLKOUTA High to A Address Valid X1 to CLKOUTA Skew X1 to CLKOUTB Skew
CLKOUTA to CLKOUTB Skew Chip Select to ARDY Low ARDY Assert to Data Valid DS Low to Data Driven DS Low to Data Valid
A
T F
A Address Valid to WHB, WLB Low
tDSHDIR tDSHDX
DS High to Data Invalid--Read DS High to Data Bus Turn-off Time
62
Am186ED/EDLV Microcontrollers
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
No. 94(a) 95(a) 96(a) 97(a) 98 99 101 102 103 104 105 106 107 108 109 110 111 Parameter Symbol tRHDZ tARYHDSH tARYLDSH tDVDSL tDSHDIW tPLAL tCHCAV tCLRA tCHRX tCHCA tCLCX tCHRA tCLRX tRP0W tRP1W tRD0W tRD1W ARDY High to DS High ARDY Low to DS High Data Valid to DS Low DS High to Data Invalid--Write PCS Active to ALE Inactive CLKOUTA Low to Column Address Valid CLKOUTA Low to RAS Active CLKOUTA High to RAS Inactive CLKOUTA High to CAS Active CLKOUTA Low to CAS Inactive CLKOUTA High to RAS Active CLKOUTA Low to RAS Inactive RAS Inactive Pulse Width (0 Wait States) RAS Inactive Pulse Width (1 Wait State) Description RD High to Data Bus Turn-off Time
RAS To Column Address Delay Time with 0 Wait States
RAS to Column Address Delay Time with 1 or More Wait States
Note: a Specs 83 and 88-97 are defined but not used at this time. Additionally, the following parameters are not defined nor used at this time: 56, 60, and 71-78.
D
R
A
T F
Am186ED/EDLV Microcontrollers
63
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Read Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 99 24 25 26 27 28 29 41 59 66 67 68 Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tPLAL tAZRL Description Data in Setup Data in Hold(c) General Timing Requirements 10 3 0 0 0 0 0 25 tCLCL -10=40 Low(a) tCLCH -2 tCHCL -2 0 tCLAX =0 0 25 25 25 25 10 3 0 0 0 0 0 20 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 24 ns ns 20 20 ns ns ns ns ns ns ns ns 20 20 ns ns 20 MHz Min Max 25 MHz Min Max Unit
General Timing Responses Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay DEN Inactive Delay 1(b)
Control Active Delay 2(b)
ALE High to Address Valid
PCS Active to ALE Inactive
Read Cycle Timing Responses tCLRL
tRLRH tCLRH tRHLH tRHAV
tDSHLH tRHDX tAVRL
D
AD Address Float to RD Active RD Active Delay RD Pulse Width
RD Inactive Delay
R
A
0 0 0 0 0 20 15 0 0 2tCLCL -15=85 0 tCLCH -3 tCLCL -10=40 tCLCH -2=21 0 tCLCL + tCHCL-3 0 0
tCLCH -2
T F
tCLCL -10=30 tCLCH -2 tCHCL -2 0 tCLAX =0 0 25 20 25 20 25 20 tCLCH -2 0 0 25 20 25 25 28 0 0 15 15 0 25 25 0 2tCLCL -15=65 0 tCLCH -3 tCLCL -10=30 tCLCH -2=16 0 tCLCL + tCHCL-3 25 25 0 0 20 20 25 0 20
RD Inactive to ALE High(a) RD Inactive to AD Address Active(a) DS Inactive to ALE Active RD High to Data Hold on AD Bus(c) A Address Valid to RD Low(a) CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid
tCHCSV tCHAV
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Read Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 99 24 25 26 27 28 29 41 59 66 67 68 Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tPLAL tAZRL tCLRL Description Data in Setup Data in Hold(c) General Timing Requirements 8 3 0 0 0 0 0 15 tCLCL -10=20 tCLCH -2 tCHCL -2 0 tCLAX =0 0 15 15 15 15 5 2 0 0 0 0 0 12 12 12 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18 ns ns 10 12 ns ns ns ns ns ns ns 10 10 ns ns 33 MHz Min Max 40 MHz Min Max Unit
General Timing Responses Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) DEN Inactive Delay Control Active Delay
15
15
15 15 15 15 20
ALE High to Address Valid
PCS Active to ALE Inactive
Read Cycle Timing Responses
tRLRH tCLRH tRHAV
tRHLH
tDSHLH tRHDX tAVRL
D
AD Address Float to RD Active RD Active Delay RD Pulse Width
RD Inactive Delay
R
2(b) Low(a)
A
0 0 0 0 0 10 12 0 0 2tCLCL -15=45 0 tCLCH -3 tCLCL -10=20 tCLCH -2=11.5 0 tCLCL + tCHCL-3 0 0
tCLCH -2
T F
tCLCL -5=20 tCLCH -2 tCHCL -2 0 tCLAX =0 0 12 12 12 tCLCH -2 0 0 12 0 0 7.5 10 0 12 12 0 12 0 2tCLCL -10=40 0 tCLCH -2 tCLCL -5=20 tCLCH -2=9.25 0 tCLCL + tCHCL-1.25 0 0
15
15 15
RD Inactive to ALE High(a) RD Inactive to AD Address Active(a) DS Inactive to ALE Active RD High to Data Hold on AD Bus(c) A Address Valid to RD CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid
tCHCSV tCHAV
15 15
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186ED/EDLV Microcontrollers
65
PRELIMINARY
READ CYCLE WAVEFORMS
t1 t2 t3 tW CLKOUTA
66
t4
A19-A0
68
Address
8
S6
(a)
S6
14
INVALID
6 1
S6
AD15-AD0 , AD7-AD0(b) AD15-AD8(b)
23 9
Address
Data
2
Address
11 15 10 24 26
ALE
RD
5
12
BHE(a)
67
LCS, UCS
16
99
MCS1-MCS0, PCS6-PCS5, PCS3-PCS0 DEN, DS
DT/R
S2-S0
D
19 22 (c) 3
R
A
13 20 4
25
BHE
T F
29 59 28 27 41 18 17 21 22 (c)
Status
UZI
Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b c Am186ED/EDLV microcontrollers in 8-bit mode Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
66
Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Write Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 99 30 31 32 33 34 35 41 65 67 68 87 98 Symbol tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tPLAL tCLDOX tCVCTX tWLWH tWHLH tWHDX Description Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R DS Inactive Delay Control Active Delay 2 ALE High to Address Valid PCS Active to ALE Inactive Data Hold Time Control Inactive WR Pulse Width Low(a) Control Active Delay 1(b) tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 tCLCL -10=40 25 General Timing Responses 0 0 0 0 0 0 25 tCLCL -10=30 25 25 25 25 15 0 0 0 0 0 0 20 20 20 20 20 20 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 ns ns ns ns ns ns ns 20 20 20 ns ns ns ns 20 MHz Min Max 25 MHz Min Max Unit
25 25 15 25
Write Cycle Timing Responses
Delay(b)
tWHDEX tDSHLH tAVWL tCHAV tAVBL
tCHCSV
D
WR Inactive to ALE
Data Hold after WR(a) WR Inactive to DEN
DS Inactive to ALE Active
R
High(a) Inactive(a)
A
0 0 20 15 0 0 2tCLCL -10=90 tCLCH -2 tCLCL -10=40 tCLCH -3 tCLCH -2=21 tCLCL+tCHCL -3 0 0 tCHCL -3 35
0
25 28
T F
tCLCH -2 tCHCL-2 0 0 20 tCLCH -2 0 0 0 20 0 15 20 0 20 15 15 0 24 0 2tCLCL -10=70 tCLCH -2 tCLCL -10=30 tCLCH -3 tCLCH -2=16 tCLCL +tCHCL -3 0 0 tCHCL -3 30
25
A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid--Write
25 25 25
tDSHDIW
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH = 2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals.
Am186ED/EDLV Microcontrollers
67
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 99 30 31 32 33 34 35 41 65 67 68 87 98 Symbol tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tPLAL tCLDOX tCVCTX tWLWH tWHLH tWHDX Description Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R DS Inactive Delay Control Active Delay 2 ALE High to Address Valid PCS Active to ALE Inactive Data Hold Time Control Inactive WR Pulse Width Low(a) Control Active Delay 1(b) tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 tCLCL -10=20 15 General Timing Responses 0 0 0 0 0 0 15 tCLCL -5=20 15 15 15 15 0 0 0 0 0 0 12 12 12 12 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 ns ns ns ns ns ns ns 10 10 12 ns ns ns ns 33 MHz Min Max 40 MHz Min Max Unit
15 15 15 15
Write Cycle Timing Responses
Delay(b)
tWHDEX tDSHLH tAVWL tCHAV tAVBL
tCHCSV
D
WR Inactive to ALE
Data Hold after WR(a) WR Inactive to DEN
DS Inactive to ALE Active
R
High(a) Inactive(a)
A
0 0 10 12 0 0 2tCLCL -10=50 tCLCH -2 tCLCL -10=20 tCLCH -3 tCLCH -2=11.5 tCLCL +tCHCL -3 0 0 tCHCL -3 20
0
15 20
T F
tCLCH -2 tCHCL-2 0 0 12 tCLCH -2 0 0 0 12 0 12 12 0 12 7.5 10 0 18 0 2tCLCL -10=40 tCLCH -2 tCLCL -10=15 tCLCH -3 tCLCH -2=9.25 tCLCL +tCHCL -1.25 0 0 tCHCL -1.25 15
15
A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid--Write
15 15 15
tDSHDIW
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals.
68
Am186ED/EDLV Microcontrollers
PRELIMINARY
WRITE CYCLE WAVEFORMS
t1 t2 t3 tW CLKOUTA
65
t4
A19-A0
68
Address
8
S6 AD15-AD0(a) AD7-AD0(b) AD15-AD8(b)
23 9
S6
14
INVALID
7
S6
30
,
Address
6
Data
Address
11 13 10
ALE
32
WR
20
12
WHB, WLB
5
87
BHE
67
LCS, UCS MCS3-MCS0, PCS6-PCS5, PCS3-PCS0 DEN
DS DT/R S2-S0
D
22
(c)
R
16
A
99 20 20
20
BHE
T F
34 31 33 41 31 18 17 35 31 98 21 19
(c)
22
Status
3 4
UZI
Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b c Am186ED/EDLV microcontrollers in 8-bit mode Changes in t phase preceding next bus cycle if followed by read, INTA, or halt
Am186ED/EDLV Microcontrollers
69
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges DRAM
Parameter No. Symbol Description General Timing Responses 101 tCHCAV CLKOUTA Low to Column Address Valid CLKOUTA Low to RAS Active 102 tCLRA 103 tCHRX CLKOUTA High to RAS Inactive CLKOUTA High to CAS Active 104 tCHCA 105 tCLCX CLKOUTA Low to CAS Inactive 106 tCHRA CLKOUTA High to RAS Active CLKOUTA Low to RAS Inactive 107 tCLRX 108 tRP0W RAS Inactive Pulse Width with 0 Wait States RAS Inactive Pulse Width with 1 or 109 tRP1W More Wait States RAS To Column Address Delay 110 tRD0W Time with 0 Wait States RAS to Column Address Delay 111 tRD1W Time with 1 or More Wait States 20 MHz Min Max 0 3 3 3 3 3 3 60 70 25 30 25 25 25 25 25 25 25 -- -- -- -- Preliminary 25 MHz 33 MHz Min Max Min Max 0 3 3 3 3 3 3 50 60 20 25 20 20 20 20 20 20 20 -- -- -- -- 0 3 3 3 3 3 3 40 50 15 20 15 15 15 15 15 15 15 -- -- -- -- 40 MHz Min Max 0 3 3 3 3 3 3 30 40 15 15 12 12 12 12 12 12 12 -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns
As guaranteed by design, the following table shows the minimum time for RAS assertion to RAS assertion. These minimums correlate to DRAM spec tRC.
0 90 110 130 150 Wait States 1 2 110 130 130 150 150 170 170 190 3 150 170 190 210
Frequency
40 MHz 33 MHz 25 MHz 20 MHz
D
70
R
A
T F
Am186ED/EDLV Microcontrollers
PRELIMINARY
DRAM Read Cycle Timing with No-Wait States
t3 t4 t1 t2 t3 t4 t1
CLKOUTA 5 AD[15:0] 68 A[17:1] Row 110 102 RAS 104 CAS 25 RD(a) Addr. 101 Column 103 15 1 Data 2
Note: a The RD output connects to the DRAM output enable (OE) pin for read operations.
DRAM Read Cycle Timing with Wait State(s)
t4
CLKOUTA
AD[15:0]
A[17:1]
RAS
D
R
t1 5 Addr. 68 Row 110 102
t2
A
t3 104 25
T F
105 27 tw t4 t1 1 Data 2 107 109 105 27
108
15
101 Column
CAS
RD(a)
Note: a The RD output connects to the DRAM output enable (OE) pin for read operations.
Am186ED/EDLV Microcontrollers
71
PRELIMINARY
DRAM Write Cycle Timing with No-Wait States t4 t1 t2 t3 t4 t1
CLKOUTA 5 AD[15:0] 68 A[17:1] Row 110 102 RAS 104 CAS 20 WR(a) Addr. 101 Column 103 7 Data 30
Note: a Write operations use the WR output connected to the DRAM write enable (WE) pin.
DRAM Write Cycle Timing With Wait State(s) t4
CLKOUTA
AD[15:0]
A[17:1]
RAS
D
68
R
t1
5 Addr. Row 102 110
t2
A
t3
Column 104 20
T F
105 31
108
tw
t4
t1
7 Data
30
101
107
109 105 CAS 31
WR(a)
Note: a Write operations use the WR output connected to the DRAM write enable (WE) pin.
72
Am186ED/EDLV Microcontrollers
PRELIMINARY
DRAM CAS-before-RAS Cycle Timing t4 t1 t2 tW tW tW t3 t4 t1
CLKOUTA 5 AD[15:0] 68 A[17:1] X 106 RAS 104 CAS(a) 25 RD(b)
FFFF
15
101 X 107
Notes: a CAS before RAS cycle timing is always 7 clocks, independent of wait state timing. b The RD output connects to the DRAM output enable (OE) pin for read operations.
D
R
A
T F
109 105 27
Am186ED/EDLV Microcontrollers
73
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. 1 2 3 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 Symbol tDVCL tCLDX tCHSV tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Description Data in Setup Data in Hold Status Active Delay Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) DEN Inactive Delay Control Active Delay Control Inactive 2(c) ALE High to Address Valid Delay(b) CLKOUTA High to A Address Valid tCLCH -2 tCLAX =0 0 0 0 0 tCLCL -10=40 General Timing Requirements 10 3 0 0 0 0 25 tCLCL -10=30 tCLCH -2 tCLAX =0 0 0 0 0 25 25 25 25 25 25 25 25 25 10 3 0 0 0 0 20 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 MHz Min Max 25 MHz Min Max Unit
General Timing Responses
25
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Testing is performed with equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals.
This parameter applies to the DEN and DT/R signals.
D
R
A
0 0
20
T F
20 20 20 20 0 20 15 0 20
74
Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. 1 2 3 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 Symbol tDVCL tCLDX tCHSV tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Description Data in Setup Data in Hold Status Active Delay Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) DEN Inactive Delay Control Active Delay 2(c) ALE High to Address Valid Control Inactive Delay(b) CLKOUTA High to A Address Valid tCLCH tCLAX =0 0 0 0 0 tCLCL -10=20 General Timing Requirements 8 3 0 0 0 0 15 tCLCL -5=20 tCLCH 0 15 15 15 15 15 15 15 15 15 5 2 0 0 0 0 12 12 12 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33 MHz Min Max 40 MHz Min Max Unit
General Timing Responses
15
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Testing is performed with equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals. This parameter applies to the DEN and DT/R signals.
D
R
A
0 0
10
T F
tCLAX =0 0 0 0 12 12 12 12 0 12 7.5 0 10
Am186ED/EDLV Microcontrollers
75
PRELIMINARY
INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS
t1
t2
t3 tW
t4
CLKOUTA
68
A19-A0
7
Address
8
S6
S6
Invalid
1 12
S6
2
(b)
AD15-AD0
15
Ptr
9
23 10 11
ALE
BHE
BHE
INTA1-INTA0
20
DEN
22
DT/R
S2-S0
Notes: a The status bits become inactive in the state preceding t4. b c d The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). This parameter applies for an interrupt acknowledge cycle that follows a write cycle. If followed by a write cycle, this change occurs in the state preceding that write cycle.
D
R
19 (c) 3
A
Status
T F
4 31 22 21 4 (a) 22 (d)
76
Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Software Halt Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. 3 4 5 9 10 11 19 22 68 Symbol tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Description Status Active Delay Status Inactive Delay AD Address Invalid Delay and BHE ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 2(b) CLKOUTA High to A Address Invalid 0 0 0 25 25 tCLCL -10=40 25 0 0 0 20 20 General Timing Responses 0 0 0 25 25 25 25 tCLCL -10=30 20 0 0 0 20 20 20 20 ns ns ns ns ns ns ns ns ns 20 MHz Min Max 25 MHz Min Max Unit
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN signal.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description
General Timing Responses 3 4 5 9 10 11 19 22 68 tCHSV tCLSH tCLAV tLHLL tCHLH tCHLL
Status Active Delay
Status Inactive Delay ALE Active Delay ALE Width
tDXDL
tCHCTV tCHAV
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN signal.
D
AD Address Invalid Delay and BHE
ALE Inactive Delay
DEN Inactive to DT/R Low(a) Control Active Delay 2(b)
R
A
Min 0 0 0 tCLCL -10=20 0 0 0
Preliminary Max
33 MHz
T F
40 MHz Min Max 15 15 15 15 tCLCL -5=20 15 0 15 15 0 0 12 10 12 0 0 0 12 12 12 12
Unit
ns ns ns ns ns ns ns ns ns
CLKOUTA High to A Address Invalid
Am186ED/EDLV Microcontrollers
77
PRELIMINARY
SOFTWARE HALT CYCLE WAVEFORMS
t1
t2
ti
ti
CLKOUTA
68
A19-A0
5
Invalid Address
S6, AD15-AD0
10
Invalid Address
ALE
9 11
DEN
19
DT/R
22 4
S2-S0
3
Status
D
78
R
A
T F
Am186ED/EDLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Clock (20 MHz and 25 MHz)
Preliminary Parameter No. 36 37 38 39 40 42 43 44 45 46 61 69 70 Symbol tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL tCLCH tCHCL tCH1CH2 tCL2CL1 tLOCK tCICOA tCICOB Description X1 Period(a) X1 Low Time (1.5 V)(a)
(a)
20 MHz Min 50 15 15 5 5 50 0.5tCLCL -2=23 0.5tCLCL -2=23 3 3 1 15 25 40 Max 60
25 MHz Min 40 15 15 5 5 Max 60 Unit ns ns ns ns ns ns ns ns ns ns ms ns ns 3 3
CLKIN Requirements
X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V) X1 Rise Time (1.0 to 3.5 V)(a) CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) CLKOUTA Fall Time (3.5 to 1.0 V) Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
CLKOUT Timing 0.5tCLCL -2=18
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
D
R
A
T F
1 15 25
0.5tCLCL -2=18
Am186ED/EDLV Microcontrollers
79
PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating ranges Clock (33 MHz and 40 MHz)
Preliminary Parameter No. 36 37 38 39 40 42 43 44 45 46 61 69 70 Symbol tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL tCLCH tCHCL tCH1CH2 tCL2CL1 tLOCK tCICOA tCICOB Description X1 Period(a) X1 Low Time (1.5 V)(a)
(a)
33 MHz Min 30 10 10 5 5 30 0.5tCLCL -1.5 =13.5 0.5tCLCL -1.5 =13.5 3 3 1 Max 60
40 MHz Min 25 7.5 7.5 5 5 25 0.5tCLCL -1.25 =11.25 0.5tCLCL -1.25 =11.25 Max 60 Unit ns ns ns ns ns ns ns ns ns ns ms ns ns 3
CLKIN Requirements
X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V) X1 Rise Time (1.0 to 3.5 V)(a) CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) CLKOUTA Fall Time (3.5 to 1.0 V) Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
CLKOUT Timing
15 25
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
D
80
R
A
T F
3 1 15 25
Am186ED/EDLV Microcontrollers
PRELIMINARY
CLOCK WAVEFORMS Clock Waveforms--Active Mode
X2
36 37 38
X1
39 40 45 46
CLKOUTA (Active, F=000)
69 42 43 44
CLKOUTB
70
Clock Waveforms--Power-Save Mode
X2
X1
CLKOUTA (Power-Save, F=010) CLKOUTB (Like X1, CBF=1) CLKOUTB (Like CLKOUTA, CBF=0)
D
R
A
T F
Am186ED/EDLV Microcontrollers
81
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Ready and Peripheral (20 MHz and 25 MHz)
Preliminary Parameter No. 47 48 49 50 51 52 53 54 55 Symbol tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV Description SRDY Transition Setup Time(a) SRDY Transition Hold Time(a)
(a)
Preliminary 25 MHz Min 10 3 10 4 6 15 10 10 Max Unit ns ns ns ns ns ns ns ns 20 ns
20 MHz Min 10 3 10 4 6 15 10 10 25 Max
Ready and Peripheral Timing Requirements
ARDY Resolution Transition Setup Time(b) ARDY Active Hold Time ARDY Setup DRQ Setup Time(a) ARDY Inactive Holding Time Peripheral Setup Time(b) Time(b)
Peripheral Timing Responses Timer Output Delay
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (33 MHz and 40 MHz)
Preliminary Parameter No. 47 48 49 50 51 52 53 54 55 Symbol tSRYCL tCLSRY tARYCH tCLARX
Ready and Peripheral Timing Requirements SRDY Transition Hold ARDY Active Hold ARDY Setup
SRDY Transition Setup Time(a) Time(a)
tARYCHL tARYLCL tINVCH tINVCL
Peripheral Timing Responses tCLTMV
D
ARDY Resolution Transition Setup Time(b) Time(a) ARDY Inactive Holding Time Time(a) Peripheral Setup Time(b) DRQ Setup Time(b) Timer Output Delay
R
Description
A
Min 8 3 8 4 6 10 8 8
T F
40 MHz Max Min 5 2 5 3 5 5 5 5 15 12 Max
33 MHz
Unit ns ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
82
Am186ED/EDLV Microcontrollers
PRELIMINARY
SYNCHRONOUS, ASYNCHRONOUS, and PERIPHERAL WAVEFORMS Synchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4 tW t3 t2 t1 tW tW t3 t2 tW tW tW t3 t4 t4 t4 t4
CLKOUTA
47
SRDY
48
Asynchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4 tW t3 t2 t1 tW tW t3
CLKOUTA ARDY (Normally NotReady System)
ARDY (Normally Ready System)
Peripheral Waveforms
D
R
53 54
A
49 49 51 52
t2
T F
tW tW tW t3 t4 t4 t4 t4
50 50 55
CLKOUTA
INT4-INT0, NMI, TMRIN1-TMRIN0 DRQ1-DRQ0
TMROUT1- TMROUT0
Am186ED/EDLV Microcontrollers
83
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Reset and Bus Hold (20 MHz and 25 MHz)
Preliminary Parameter No. 5 15 57 58 62 63 64 Symbol tCLAV tCLAZ tRESIN tHVCL tCLHAV tCHCZ tCHCV Description AD Address Valid Delay and BHE AD Address Float Delay RES Setup Time HOLD Setup(a) HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) Reset and Bus Hold Timing Requirements 0 0 10 10 0 25 25 25 25 25 0 0 10 10 0 20 20 20 20 20 ns ns ns ns ns ns ns 20 MHz Min Max 25 MHz Min Max Unit
Reset and Bus Hold Timing Responses
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Reset and Bus Hold (33 MHz and 40 MHz)
Preliminary Parameter No. 5 15 57 58 62 63 64 Symbol tCLAV tCLAZ tRESIN tHVCL tCLHAV tCHCZ tCHCV Description AD Address Valid Delay and BHE AD Address Float Delay RES Setup Time HOLD Setup(a) HLDA Valid Delay Reset and Bus Hold Timing Requirements 33 MHz Min
Reset and Bus Hold Timing Responses
Command Lines Float Delay
Command Lines Valid Delay (after Float)
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a This timing must be met to guarantee recognition at the next clock.
D
R
A
0 0 8 8 0
T F
40 MHz Max 15 15 Min 0 0 Max 12 12 5 5 15 15 15 0 12 12 12
Unit ns ns ns ns ns ns ns
84
Am186ED/EDLV Microcontrollers
PRELIMINARY
RESET and BUS HOLD WAVEFORMS Reset Waveforms
X1
57 57
RES
CLKOUTA
Signals Related to Reset Waveforms
RES
S2/BTSEL, CLKOUTA BHE/ADEN, S6/CLKDIV2, and UZI
AD15-AD0
D
R
A
Three-State
T F
Three-State
Am186ED/EDLV Microcontrollers
85
PRELIMINARY
Bus Hold Waveforms--Entering
Case 1 Case 2 ti t4 ti ti ti ti
CLKOUTA
58
HOLD
62
HLDA
15
AD15-AD0, DEN A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
63
Bus Hold Waveforms--Leaving
Case 1 Case 2 ti ti
CLKOUTA
HOLD
HLDA
AD15-AD0, DEN A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
D
R
58
A
ti ti
62
T F
ti t1 t1 t4
5 64
86
Am186ED/EDLV Microcontrollers
PRELIMINARY
TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack
100
1
15.80 16.20 13.80 14.20
13.80 14.20
1.35 1.45
D
1.00 REF.
R
0.50 BSC
15.80 16.20
A
T F
16-038-PQT-2_AI PQL100 9.3.96 lv
11 - 13 1.60 MAX
11 - 13
0.17 0.27
Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only.
Am186ED/EDLV Microcontrollers
87
PRELIMINARY
PQFP PHYSICAL DIMENSIONS PQR 100, Trimmed and Formed Plastic Quad Flat Pack
17.00 17.40
Pin 100
12.35 REF
13.90 14.10
Pin 80
Pin 1 I.D.
Pin 30
2.70 2.90 0.25 MIN
D
R
0.65 BASIC
A
T F
18.85 REF 19.90 20.10 23.00 23.40 3.35 MAX SEATING PLANE
16-038-PQR-1_AH PQR100 DP92 6-20-96 lv
Pin 50
Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only.
Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. Am186, Am188, E86, K86, Elan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
88
Am186ED/EDLV Microcontrollers

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